MyHDL signal delay argument

signal_delay.py

from myhdl import *
import myhdl_tools as mt

def m_add(a, b, c):
    @always_comb
    def rtl():
        c.next = a and b
    return rtl

def test():
    a = Signal(bool(0), delay=10)
    b = Signal(bool(0), delay=1)
    c = Signal(bool(0))
    def _test():
        tbdut = m_add(a, b, c)
        
        @instance
        def tbstim():
            yield delay(100)
            a.next = True
            b.next = True
            yield delay(100)
        return tbdut, tbstim

    g = traceSignals(_test)
    Simulation(g).run()
    fig,ax = mt.vcd.parse_and_plot('_test.vcd')
    fig.savefig('signal_delay.png')

test()