test that demonstrates the interface conversion error in the myhdl tip

test_interfaces4.py

from myhdl import *

"""
This set of tests exercies a peculiar scenario where an
expanded interface is Signal is flagged as having multiple
drivers.  This appears to be a name collision in the name
expansion and was introduced in ....
"""

class Intf1(object):
    def __init__(self):
        self.sig1 = Signal(bool(0))
        self.sig2 = Signal(bool(0))
        self.sig3 = Signal(intbv(0)[8:])


class Intf2(object):
    def __init__(self):
        self.sig1 = Signal(bool(0))
        self.sig2 = Signal(bool(0))
        self.sig3 = Signal(intbv(0)[8:])
        self.intf = Intf1()


def mod1(clock, reset, intf1, intf2):
    
    sig1 = Signal(bool(0))
    sig2 = Signal(bool(0))
    @always_seq(clock.posedge, reset)
    def proc():
        if intf1.sig1:
            sig1.next = True
            sig2.next = False
        else:
            sig1.next = False
            sig2.next = True

        intf2.sig1.next = sig1
        intf2.sig2.next = sig2 or intf1.sig2
        intf2.sig3.next = ~intf1.sig3

    return proc


def mod2(clock, reset, intf1, intf2):
    @always_seq(clock.posedge, reset)
    def proc():
        # remove the if/else and leave just the line in the
        # if clause the error does not occur, inlcude the if/else
        # and the error occurs
        if intf1.sig3 > 0:        # remove no error
            intf2.sig1.next = not intf1.sig1
            intf2.sig2.next = not intf1.sig2
            intf2.sig3.next = intf1.sig3 + intf2.sig3
        else:                     # remove no error
            intf2.sig3.next = 0   # remove no error

    return proc


def top(clock, reset, sdi, sdo):
    
    intf1 = Intf1()
    intf2 = Intf2()
    intf3 = Intf1()

    g1 = mod1(clock, reset, intf1, intf2)
    g2 = mod2(clock, reset, intf2, intf3)

    @always_seq(clock.posedge, reset)
    def assigns():
        intf1.sig1.next = sdi
        intf1.sig2.next = not sdi
        intf1.sig3.next = concat(intf1.sig3[7:1], sdi)
        sdo.next = intf3.sig1 | intf3.sig2 | intf3.sig3[2]

    return g1, g2, assigns


def convert():
    clock = Signal(bool(0))
    reset = ResetSignal(0, active=1, async=False)
    sdi = Signal(bool(0))
    sdo = Signal(bool(0))
    toVerilog(top, clock, reset, sdi, sdo)
    toVHDL(top, clock, reset, sdi, sdo)


if __name__ == '__main__':
    convert()
    

zzz_vhdl.vhd

-- File: top.vhd
-- Generated by MyHDL 1.0dev
-- Date: Wed Sep  2 08:27:06 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_10.all;

entity top is
    port (
        clock: in std_logic;
        reset: in std_logic;
        sdi: in std_logic;
        sdo: out std_logic
    );
end entity top;


architecture MyHDL of top is





signal intf3_sig2: std_logic;
signal intf3_sig1: std_logic;
signal intf1_sig2: std_logic;
signal intf1_sig3: unsigned(7 downto 0);
signal intf3_sig3: unsigned(7 downto 0);
signal intf1_sig1: std_logic;
signal g2_intf1_sig2: std_logic;
signal g2_intf1_sig3: unsigned(7 downto 0);
signal g2_intf1_sig1: std_logic;
signal g1_sig1: std_logic;
signal g1_sig2: std_logic;

begin





TOP_G1_PROC: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            g1_sig1 <= '0';
            g2_intf1_sig1 <= '0';
            g1_sig2 <= '0';
            g2_intf1_sig2 <= '0';
            g2_intf1_sig3 <= to_unsigned(0, 8);
        else
            if bool(intf1_sig1) then
                g1_sig1 <= '1';
                g1_sig2 <= '0';
            else
                g1_sig1 <= '0';
                g1_sig2 <= '1';
            end if;
            g2_intf1_sig1 <= g1_sig1;
            g2_intf1_sig2 <= stdl(bool(g1_sig2) or bool(intf1_sig2));
            g2_intf1_sig3 <= (not intf1_sig3);
        end if;
    end if;
end process TOP_G1_PROC;


TOP_G2_PROC: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            intf3_sig1 <= '0';
            intf3_sig2 <= '0';
            intf3_sig3 <= to_unsigned(0, 8);
        else
            if (g2_intf1_sig3 > 0) then
                intf3_sig1 <= stdl((not bool(g2_intf1_sig1)));
                intf3_sig2 <= stdl((not bool(g2_intf1_sig2)));
                intf3_sig3 <= (g2_intf1_sig3 + intf3_sig3);
            else
                intf3_sig3 <= to_unsigned(0, 8);
            end if;
        end if;
    end if;
end process TOP_G2_PROC;


TOP_ASSIGNS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            intf1_sig2 <= '0';
            intf1_sig3 <= to_unsigned(0, 8);
            sdo <= '0';
            intf1_sig1 <= '0';
        else
            intf1_sig1 <= sdi;
            intf1_sig2 <= stdl((not bool(sdi)));
            intf1_sig3 <= resize(unsigned'(intf1_sig3(7-1 downto 1) & sdi), 8);
            sdo <= ((intf3_sig1 or intf3_sig2) or intf3_sig3(2));
        end if;
    end if;
end process TOP_ASSIGNS;

end architecture MyHDL;