rapid modeling - break the ice

spi_master_model.py

from __future__ import division
from __future__ import print_function

from myhdl import *

from zintf import IBus
from zintf import SPIBus
from spi_slave import SPISlave


def m_spi_controller_model(clock, reset, ibus, spibus):
    """

      ibus   : internal bus
      spibus : SPI interface (SPIBus)
    """

    @instance
    def decode_ibus():
        while True:
            yield clock.posedge
            ibus.ack.next = False  # default value

            if ibus.wr:
                yield spibus.writeread(ibus.data_in)
                ibus.ack.next = True
            elif ibus.rd:
                yield spibus.writeread(0x55)
                ibus.data_out.next = spibus.ival
                ibus.ack.next = True


    return decode_ibus


def test():
    clock = Signal(bool(0))
    reset = ResetSignal(0, active=1, async=False)
    ibus = IBus(clock, reset)
    spibus = SPIBus()

    def _test():
        
        tbdut = m_spi_controller_model(clock, reset, ibus, spibus)
        tbspi = SPISlave().process(spibus)


        @always(delay(3))
        def tbclk():
            clock.next = not clock

        @instance
        def tbstim():
            reset.next = reset.active
            yield delay(33)
            yield clock.posedge
            reset.next = not reset.active
            yield delay(13)
            yield clock.posedge

            yield ibus.write(0xBE)
            yield delay(100)
            yield ibus.read()

            raise StopSimulation

        return tbdut, tbspi, tbclk, tbstim

    g = traceSignals(_test)
    Simulation(g).run()


if __name__ == '__main__':
    test()
                

spi_slave.py

from __future__ import division
from __future__ import print_function

from myhdl import *

from zintf import SPIBus

class SPISlave(object):
    def __init__(self):
        self.reg = intbv(0)[8:]

    def process(self, spibus):
        mosi = spibus.mosi
        miso = spibus.miso
        sck = spibus.sck 
        csn = spibus.csn

        @instance
        def gproc():
            while True:
                yield csn.negedge                
                bcnt = 8
                while not csn:
                    if bcnt > 0:
                        miso.next = self.reg[bcnt-1]
                        yield sck.posedge
                        bcnt -= bcnt
                        self.reg[bcnt] = mosi
                    else:
                        yield delay(10)

        return gproc
                

zintf.py

from myhdl import *

class IBus(object):
    def __init__(self, clock, reset):
        self.clock = clock
        self.reset = reset
        self.wr = Signal(bool(0))  # write strobe
        self.rd = Signal(bool(0))  # read strobe
        self.data_in = Signal(intbv(0)[8:])
        self.data_out = Signal(intbv(0)[8:])
        self.address = Signal(intbv(0)[20:])
        self.ack = Signal(bool(0))

        # place to hold the return value
        self.rval = None

    def write(self, val):
        yield self.clock.posedge
        self.wr.next = True
        self.data_in.next = val
        while not self.ack:
            yield self.clock.posedge
        self.wr.next = False

    def read(self):
        yield self.clock.posedge
        self.rd.next = True
        while not self.ack:
            yield self.clock.posedge
        self.rval = self.data_out
        self.rd.next = False

        
class SPIBus(object):
    def __init__(self):
        self.htck = 234
        self.mosi = Signal(bool(0))
        self.miso = Signal(bool(0))
        self.sck = Signal(bool(0))
        self.csn = Signal(bool(1))
        
        self.oval = intbv(0)[8:]
        self.ival = intbv(0)[8:]


    def writeread(self, val):
        htck = self.htck
        self.oval[:] = val
        self.csn.next = False
        yield delay(htck//2)
        for ii in range(7, -1, -1):
            self.sck.next = False
            self.mosi.next = self.oval[ii]
            yield delay(htck)
            self.sck.next = True
            yield delay(3)
            self.ival[ii] = self.miso
            yield delay(htck-3)

        self.csn.next = True
        yield delay(htck)