Example of an interface property conversion

intf_propattr.py

from myhdl import *

class Intf(object):
    def __init__(self):
        self.a = Signal(intbv(0)[8:])
        self.b = Signal(intbv(0)[8:])
        self._x = Signal(intbv(0)[8:])
    
    @property
    def c(self):
        return self._x

def m_propattr(intf1, intf2):
    @always_comb
    def rtl():
        intf1.a.next = intf2.c
    return rtl

intf1 = Intf()
intf2 = Intf()
toVerilog(m_propattr, intf1, intf2)

m_propattr.v

// File: m_propattr.v
// Generated by MyHDL 0.9.dev0
// Date: Sat Apr  4 09:51:24 2015


`timescale 1ns/10ps

module m_propattr (
    intf1_a,
    intf1_b,
    intf1__x,
    intf2_a,
    intf2_b,
    intf2_c
);


output [7:0] intf1_a;
wire [7:0] intf1_a;
input [7:0] intf1_b;
input [7:0] intf1__x;
input [7:0] intf2_a;
input [7:0] intf2_b;
input [7:0] intf2_c;


assign intf1_a = intf2_c;

endmodule