MyHDL toVHDL name conflicts (reported by others) works with vcom fails with GHDL.

name_conflicts.py

from random import randint
from myhdl import *

def pipe(xi, xo, clock, reset, N=8):

    buffer = [Signal(xi.val) for _ in range(N)]

    @always_seq(clock.posedge, reset=reset)
    def rtl():
        buffer[0].next = xi
        for n in range(1, N):
            buffer[n].next = buffer[n-1]
        xo.next = buffer[N-1]

    return rtl


def tb_pipe(N=8):
    clock = Signal(bool(0))
    reset = ResetSignal(0, active=1, async=False)
    xi = Signal(intbv(0, min=-8, max=8))
    xo = Signal(intbv(0, min=-8, max=8))

    tbdut = pipe(xi, xo, clock, reset, N=N)
    
    @instance
    def tbclk():
        clock.next = False
        while True:
            yield delay(5)
            clock.next = not clock
            
    # required for testbench conversion
    reset_active = reset.active
    val = randint(-7, 7)
    @instance
    def tbstim():
        reset.next = reset_active
        yield delay(33)
        yield clock.posedge
        reset.next = not reset_active

        xi.next = val

        for ii in range(N+2):
            yield clock.posedge
            xi.next = 0
        print("%d, %d == %d" % (xi, xo, val))
        assert xo == val
        yield delay(40)
        raise StopSimulation

    return tbdut, tbclk, tbstim


def test():
    Simulation(traceSignals(tb_pipe)).run()
    print("testbench success")

    clock = Signal(bool(0))
    reset = ResetSignal(0, active=1, async=False)
    xi = Signal(intbv(0, min=-8, max=8))
    xo = Signal(intbv(0, min=-8, max=8))
    toVHDL(pipe, xi, xo, clock, reset)
    print("DUT conversion success")
    toVHDL(tb_pipe)
    print("testbench conversion success")


def test_analyze():
    assert conversion.analyze(tb_pipe) == 0


def test_verify():
    assert conversion.verify(tb_pipe) == 0


if __name__ == '__main__':
    conversion.verify.simulator = conversion.analyze.simulator = 'GHDL'
    test()
    test_analyze()
    test_verify()