another tri-state example

tristate_ya.py

from random import randint
from myhdl import *


def tristate(tri, tin, tout, en):
    """ tristate driver
    Ports:
      tri: tri-state signal
      tin: tri-state input
      tout: the signal to drive the tri-state
      en: enable the tri-state for driving
    """
    #assert isinstance(tri, TristateSignal)
    tridrv = tri.driver()

    @always_comb
    def input():
        tin.next = bool(tri)

    @always_comb
    def output():
        if en:
            tridrv.next = tout
        else:
            tridrv.next = None

    return input, output
    

def tristate_tb(num_drivers=3, num_loops=13):
    tri = TristateSignal(bool(0))
    ti = [Signal(bool(0)) for _ in range(num_drivers)]
    to = [Signal(bool(0)) for _ in range(num_drivers)]
    en = [Signal(bool(0)) for _ in range(num_drivers)]
    tri_inst = []
    for ii in range(num_drivers):
        tri_inst.append(tristate(tri, ti[ii], to[ii], en[ii]))
    
    @instance
    def tb():
        yield delay(10)
        assert tri == None  # needs to be "==" and not "is"
        for ii in range(num_loops):
            tdrv = randint(0, num_drivers-1)
            tval = randint(0, 1)
            to[tdrv].next = bool(tval)
            en[tdrv].next = True
            yield delay(1)
            assert tri == to[tdrv]
            en[tdrv].next = False
            
        yield delay(10)
        
    return instances()

tri = TristateSignal(bool(0))
ti = Signal(bool(0))
to = Signal(bool(0))
en = Signal(bool(0))

Simulation(traceSignals(tristate_tb)).run()
toVHDL(tristate, tri, ti, to, en)

zzz_tristate.vhd

-- File: tristate.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon Oct 26 07:15:17 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_10.all;

entity tristate is
    port (
        tri: inout std_logic;
        tin: out std_logic;
        tout: in std_logic;
        en: in std_logic
    );
end entity tristate;
-- tristate driver
-- Ports:
--   tri: tri-state signal
--   tin: tri-state input
--   tout: the signal to drive the tri-state
--   en: enable the tri-state for driving

architecture MyHDL of tristate is



signal tridrv: std_logic;

begin



tri <= tridrv;



tin <= tri;


TRISTATE_OUTPUT: process (en, tout) is
begin
    if bool(en) then
        tridrv <= tout;
    else
        tridrv <= 'Z';
    end if;
end process TRISTATE_OUTPUT;

end architecture MyHDL;