huyng

### MATPLOTLIBRC FORMAT

# This is a sample matplotlib configuration file - you can find a copy
# of it on your system in
# site-packages/matplotlib/mpl-data/matplotlibrc.  If you edit it
# there, please note that it will be overridden in your next install.
# If you want to keep a permanent local copy that will not be
# over-written, place it in HOME/.matplotlib/matplotlibrc (unix/linux
# like systems) and C:\Documents and Settings\yourname\.matplotlib
# (win32 systems).

cfelton

from random import randint
from myhdl import *

class MemPort:
    def __init__(self,depth=128):
        self.addr = Signal(modbv(0, min=0, max=depth))
        self.wdata = Signal(intbv(0)[8:])
        self.we = Signal(bool(0))
        self.rdata = Signal(intbv(0)[8:])
    def get_signals(self):

cfelton

from myhdl import *

def simple_add(a,b,):
    c = a + b
    return c

def top(clock,reset,a,b,c):
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        c.next = simple_add(a,b)

ravijain056

from myhdl import *

def switchchannels(mem2d, q, clk):

    def assign_los(mem1d_a, mem1d_b):
        print(mem1d_a, mem1d_b)
        for i in range(len(mem1d_a)):
            mem1d_a[i].next = mem1d_b[i]
        return mem1d_a

j-marjanovic

Introduction

This code snippet demonstrates a co-simulation of Verilog code and MyHDL code. The three modules here presents the absolute minimum for a co-simulation.

The counter_top.v is the top level module. It instantiates the counter module (found in file counter.v), which is the module we would like to evaluate. Also instantiated are the signals which are feed from and to MyHDL.

mkatsimpris

 
  constant C_Y_1       : signed(14 downto 0) := to_signed(4899,  15);
  constant C_Y_2       : signed(14 downto 0) := to_signed(9617,  15);
  constant C_Y_3       : signed(14 downto 0) := to_signed(1868,  15);
  constant C_Cb_1      : signed(14 downto 0) := to_signed(-2764, 15);
  constant C_Cb_2      : signed(14 downto 0) := to_signed(-5428, 15);
  constant C_Cb_3      : signed(14 downto 0) := to_signed(8192,  15);
  constant C_Cr_1      : signed(14 downto 0) := to_signed(8192,  15);
  constant C_Cr_2      : signed(14 downto 0) := to_signed(-6860, 15);
  constant C_Cr_3      : signed(14 downto 0) := to_signed(-1332, 15);