mkatsimpris

sudo apt-get update
sudo apt-get install git libzmq3-dev libssl-dev build-essential cmake pkg-config libsodium-dev libminiupnpc-dev liblzma-dev libreadline6-dev libldns-dev libexpat1-dev libgtest-dev libboost-all-dev libunbound-dev graphviz doxygen libunwind8-dev
git clone --recursive https://github.com/monero-project/monero
cd monero/
make

mkatsimpris

\begin{figure}[H]
  \centering
  \begin{tikzpicture}
    \begin{axis}[
        width=15cm,
        height=15cm,
        title={Combinational area results},
        xlabel={Clock Period[ns]},
        ylabel={Area[NAND-2 GE]},
        xmin=1, xmax=4,

mkatsimpris

-- File: pck_myhdl_10.vhd
-- Generated by MyHDL 1.0dev
-- Date: Tue Aug  2 17:02:03 2016


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package pck_myhdl_10 is

mkatsimpris

-- File: frontend_top_level_v2.vhd
-- Generated by MyHDL 1.0dev
-- Date: Tue Aug  2 17:02:03 2016


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

mkatsimpris

Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
| Date         : Sat Jul 23 10:58:51 2016
| Host         : VLSILAB-STRIKE running 64-bit Service Pack 1  (build 7601)
| Command      : report_utilization -file frontend_top_level_v2_utilization_synth.rpt -pb frontend_top_level_v2_utilization_synth.pb
| Design       : frontend_top_level_v2
| Device       : xc7vx690t
| Design State : Synthesized
-------------------------------------------------------------------------------------------------------------------------------------

mkatsimpris

#-----------------------------------------------------------
# Vivado v2014.4 (64-bit)
# SW Build 1071353 on Tue Nov 18 18:29:27 MST 2014
# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
# Start of session at: Sat Jul 23 10:57:45 2016
# Process ID: 400
# Log file: C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.runs/synth_1/frontend_top_level_v2.vds
# Journal file: C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source frontend_top_level_v2.tcl

mkatsimpris

#!/usr/bin/env python
# coding=utf-8

import numpy as np
from math import sqrt, pi, cos
import myhdl
from myhdl import Signal, ResetSignal, intbv, always_comb, always_seq, ConcatSignal
from myhdl.conversion import analyze
from jpegenc.subblocks.common import (input_interface,
                                      output_interface)

mkatsimpris

@myhdl.block
def dct_2d(inputs, outputs, clock, reset, num_fractional_bits=14):

    first_1d_output = output_interface()

    first_1d = dct_1d(inputs, first_1d_output, clock,
                      reset, num_fractional_bits)

    inputs_2nd_stage = [input_1d_2nd_stage(first_1d_output.out_precision)
                        for _ in range(8)]

mkatsimpris

1)N=bits pou prepei na athroisw kai input to shma mou
2) exw ena component enan adder me inputs:a,b kai output:c=====> adder(a,b,c)
3) exw array apo signals gia na ta exw ekei gia na ginei swsta to port map. kanw assign ekei ta outputs ton adders. 
este oti to leme out array. epishs to megethos tou einai N-1 kai exei ta outputs twn endiameswn adders. esy tha oriseis to bitwidth.
gia n>4
for i in 0 to log2(N) - 2:
  for j in 0 to N/2 - 2*i - 1:
      if i==0 generate:
          adder(input(2*j),input(2*j+1),out(j))
      else generate:

mkatsimpris

#!/usr/bin/env python
# coding=utf-8


from myhdl import *
from myhdl.conversion import *
from random import randrange

const = [-2, -3]