frontend_v2.vhd

-- File: frontend_top_level_v2.vhd
-- Generated by MyHDL 1.0dev
-- Date: Tue Aug  2 17:02:03 2016


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_10.all;

entity frontend_top_level_v2 is
    port (
        clock: in std_logic;
        reset: in std_logic;
        outputs_data_out: out signed (10 downto 0);
        outputs_end_of_block_conversion: in std_logic;
        outputs_data_valid: out std_logic;
        inputs_color_mode: in unsigned(1 downto 0);
        inputs_green: in unsigned(7 downto 0);
        inputs_data_valid: in std_logic;
        inputs_blue: in unsigned(7 downto 0);
        inputs_red: in unsigned(7 downto 0)
    );
end entity frontend_top_level_v2;
-- Inputs:red, green , blue, data_valid
-- Outputs: data_out

architecture MyHDL of frontend_top_level_v2 is


signal start_out: std_logic;
signal inputs_reg_blue: unsigned(7 downto 0);
signal zig_zag_out_data_valid: std_logic;
signal inputs_reg_data_valid: std_logic;
signal inputs_reg_green: unsigned(7 downto 0);
signal dct_2d_input_data_in: unsigned(7 downto 0);
signal rgb2ycbcr_out_data_out: unsigned(7 downto 0);
signal dct_2d_input_data_valid: std_logic;
signal inputs_reg_red: unsigned(7 downto 0);
signal output_counter: unsigned(5 downto 0);
signal rgb2ycbcr_out_data_valid: std_logic;
signal inputs_reg_color_mode: unsigned(1 downto 0);
signal input_counter: unsigned(5 downto 0);
signal color_mode: unsigned(1 downto 0);
signal rgb2ycbcr_v2_1_color_mode_reg_1: unsigned(1 downto 0);
signal rgb2ycbcr_v2_1_third_adder_sum: signed (23 downto 0);
signal rgb2ycbcr_v2_1_first_adder_sum: signed (23 downto 0);
signal rgb2ycbcr_v2_1_B_s: signed (8 downto 0);
signal rgb2ycbcr_v2_1_R_s: signed (8 downto 0);
signal rgb2ycbcr_v2_1_second_adder_sum: signed (23 downto 0);
signal rgb2ycbcr_v2_1_color_mode_reg: unsigned(1 downto 0);
signal rgb2ycbcr_v2_1_G_s: signed (8 downto 0);
signal zig_zag_1_inputs_data_valid: std_logic;
signal zig_zag_1_assign_array_11_assign_218_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_219_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_220_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_221_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_222_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_223_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_224_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_225_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_226_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_227_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_228_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_229_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_230_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_231_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_232_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_233_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_234_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_235_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_236_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_237_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_238_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_239_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_240_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_241_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_242_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_243_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_244_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_245_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_246_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_247_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_248_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_249_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_250_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_251_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_252_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_253_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_254_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_255_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_256_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_257_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_258_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_259_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_260_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_261_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_262_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_263_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_264_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_265_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_266_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_267_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_268_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_269_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_270_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_271_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_272_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_273_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_274_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_275_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_276_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_277_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_278_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_279_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_280_b: signed (10 downto 0);
signal zig_zag_1_assign_array_11_assign_281_b: signed (10 downto 0);
signal dct_2d_1_data_in_signed: signed (8 downto 0);
signal dct_2d_1_input_1d_stage_1_data_valid: std_logic;
signal dct_2d_1_outputs_data_valid: std_logic;
signal dct_2d_1_data_valid_reg2: std_logic;
signal dct_2d_1_counter: unsigned(2 downto 0);
signal dct_2d_1_input_1d_stage_1_data_in: signed (8 downto 0);
signal dct_2d_1_data_valid_reg: std_logic;
signal dct_2d_1_dct_1d_2_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_2_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_2_data_in_reg: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_first_row_passed: std_logic;
signal dct_2d_1_dct_1d_2_output_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_2_input_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_2_input_interface_data_in: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_assign_array_2_assign_9_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_assign_array_2_assign_10_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_assign_array_2_assign_11_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_assign_array_2_assign_12_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_assign_array_2_assign_13_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_assign_array_2_assign_14_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_assign_array_2_assign_15_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_2_assign_array_2_assign_16_a: signed (10 downto 0);
signal dct_2d_1_assign_17_b: signed (10 downto 0);
signal dct_2d_1_assign_18_b: std_logic;
signal dct_2d_1_dct_1d_3_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_3_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_3_data_in_reg: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_first_row_passed: std_logic;
signal dct_2d_1_dct_1d_3_output_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_3_input_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_3_input_interface_data_in: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_assign_array_3_assign_27_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_assign_array_3_assign_28_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_assign_array_3_assign_29_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_assign_array_3_assign_30_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_assign_array_3_assign_31_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_assign_array_3_assign_32_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_assign_array_3_assign_33_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_3_assign_array_3_assign_34_a: signed (10 downto 0);
signal dct_2d_1_assign_35_b: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_4_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_4_data_in_reg: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_first_row_passed: std_logic;
signal dct_2d_1_dct_1d_4_output_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_4_input_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_4_input_interface_data_in: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_assign_array_4_assign_45_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_assign_array_4_assign_46_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_assign_array_4_assign_47_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_assign_array_4_assign_48_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_assign_array_4_assign_49_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_assign_array_4_assign_50_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_assign_array_4_assign_51_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_4_assign_array_4_assign_52_a: signed (10 downto 0);
signal dct_2d_1_assign_53_b: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_5_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_5_data_in_reg: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_first_row_passed: std_logic;
signal dct_2d_1_dct_1d_5_output_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_5_input_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_5_input_interface_data_in: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_assign_array_5_assign_63_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_assign_array_5_assign_64_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_assign_array_5_assign_65_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_assign_array_5_assign_66_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_assign_array_5_assign_67_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_assign_array_5_assign_68_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_assign_array_5_assign_69_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_5_assign_array_5_assign_70_a: signed (10 downto 0);
signal dct_2d_1_assign_71_b: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_6_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_6_data_in_reg: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_first_row_passed: std_logic;
signal dct_2d_1_dct_1d_6_output_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_6_input_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_6_input_interface_data_in: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_assign_array_6_assign_81_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_assign_array_6_assign_82_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_assign_array_6_assign_83_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_assign_array_6_assign_84_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_assign_array_6_assign_85_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_assign_array_6_assign_86_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_assign_array_6_assign_87_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_6_assign_array_6_assign_88_a: signed (10 downto 0);
signal dct_2d_1_assign_89_b: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_7_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_7_data_in_reg: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_first_row_passed: std_logic;
signal dct_2d_1_dct_1d_7_output_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_7_input_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_7_input_interface_data_in: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_assign_array_7_assign_99_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_assign_array_7_assign_100_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_assign_array_7_assign_101_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_assign_array_7_assign_102_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_assign_array_7_assign_103_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_assign_array_7_assign_104_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_assign_array_7_assign_105_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_7_assign_array_7_assign_106_a: signed (10 downto 0);
signal dct_2d_1_assign_107_b: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_8_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_8_data_in_reg: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_first_row_passed: std_logic;
signal dct_2d_1_dct_1d_8_output_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_8_input_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_8_input_interface_data_in: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_assign_array_8_assign_117_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_assign_array_8_assign_118_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_assign_array_8_assign_119_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_assign_array_8_assign_120_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_assign_array_8_assign_121_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_assign_array_8_assign_122_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_assign_array_8_assign_123_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_8_assign_array_8_assign_124_a: signed (10 downto 0);
signal dct_2d_1_assign_125_b: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_9_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_9_data_in_reg: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_first_row_passed: std_logic;
signal dct_2d_1_dct_1d_9_output_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_9_input_interface_data_valid: std_logic;
signal dct_2d_1_dct_1d_9_input_interface_data_in: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_assign_array_9_assign_135_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_assign_array_9_assign_136_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_assign_array_9_assign_137_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_assign_array_9_assign_138_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_assign_array_9_assign_139_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_assign_array_9_assign_140_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_assign_array_9_assign_141_a: signed (10 downto 0);
signal dct_2d_1_dct_1d_9_assign_array_9_assign_142_a: signed (10 downto 0);
signal dct_2d_1_assign_143_b: signed (10 downto 0);
signal dct_2d_1_dct_1d_1_cycles_counter: unsigned(3 downto 0);
signal dct_2d_1_dct_1d_1_inputs_counter: unsigned(2 downto 0);
signal dct_2d_1_dct_1d_1_data_in_reg: signed (8 downto 0);
signal dct_2d_1_dct_1d_1_first_row_passed: std_logic;
type t_array_zig_zag_out_out_sigs is array(0 to 64-1) of signed (10 downto 0);
signal zig_zag_out_out_sigs: t_array_zig_zag_out_out_sigs;
type t_array_rgb2ycbcr_v2_1_mul_reg_1 is array(0 to 3-1) of signed (23 downto 0);
signal rgb2ycbcr_v2_1_mul_reg_1: t_array_rgb2ycbcr_v2_1_mul_reg_1;
type t_array_rgb2ycbcr_v2_1_mul_reg is array(0 to 3-1) of signed (23 downto 0);
signal rgb2ycbcr_v2_1_mul_reg: t_array_rgb2ycbcr_v2_1_mul_reg;
type t_array_rgb2ycbcr_v2_1_data_valid_reg is array(0 to 4-1) of std_logic;
signal rgb2ycbcr_v2_1_data_valid_reg: t_array_rgb2ycbcr_v2_1_data_valid_reg;
type t_array_rgb2ycbcr_v2_1_offset is array(0 to 3-1) of signed (23 downto 0);
signal rgb2ycbcr_v2_1_offset: t_array_rgb2ycbcr_v2_1_offset;
type t_array_rgb2ycbcr_v2_1_coeffs is array(0 to 3-1) of signed (14 downto 0);
signal rgb2ycbcr_v2_1_coeffs: t_array_rgb2ycbcr_v2_1_coeffs;
type t_array_zig_zag_1_input_sigs is array(0 to 64-1) of signed (10 downto 0);
signal zig_zag_1_input_sigs: t_array_zig_zag_1_input_sigs;
type t_array_zig_zag_1_output_sigs is array(0 to 64-1) of signed (10 downto 0);
signal zig_zag_1_output_sigs: t_array_zig_zag_1_output_sigs;
type t_array_dct_2d_1_dct_1d_2_mux_flush is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_2_mux_flush: t_array_dct_2d_1_dct_1d_2_mux_flush;
type t_array_dct_2d_1_dct_1d_2_mult_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_2_mult_reg: t_array_dct_2d_1_dct_1d_2_mult_reg;
type t_array_dct_2d_1_dct_1d_2_adder_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_2_adder_reg: t_array_dct_2d_1_dct_1d_2_adder_reg;
type t_array_dct_2d_1_dct_1d_2_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_2_output_sigs: t_array_dct_2d_1_dct_1d_2_output_sigs;
type t_array_dct_2d_1_dct_1d_2_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_2_coeffs: t_array_dct_2d_1_dct_1d_2_coeffs;
type t_array_dct_2d_1_dct_1d_3_mux_flush is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_3_mux_flush: t_array_dct_2d_1_dct_1d_3_mux_flush;
type t_array_dct_2d_1_dct_1d_3_mult_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_3_mult_reg: t_array_dct_2d_1_dct_1d_3_mult_reg;
type t_array_dct_2d_1_dct_1d_3_adder_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_3_adder_reg: t_array_dct_2d_1_dct_1d_3_adder_reg;
type t_array_dct_2d_1_dct_1d_3_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_3_output_sigs: t_array_dct_2d_1_dct_1d_3_output_sigs;
type t_array_dct_2d_1_dct_1d_3_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_3_coeffs: t_array_dct_2d_1_dct_1d_3_coeffs;
type t_array_dct_2d_1_dct_1d_4_mux_flush is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_4_mux_flush: t_array_dct_2d_1_dct_1d_4_mux_flush;
type t_array_dct_2d_1_dct_1d_4_mult_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_4_mult_reg: t_array_dct_2d_1_dct_1d_4_mult_reg;
type t_array_dct_2d_1_dct_1d_4_adder_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_4_adder_reg: t_array_dct_2d_1_dct_1d_4_adder_reg;
type t_array_dct_2d_1_dct_1d_4_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_4_output_sigs: t_array_dct_2d_1_dct_1d_4_output_sigs;
type t_array_dct_2d_1_dct_1d_4_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_4_coeffs: t_array_dct_2d_1_dct_1d_4_coeffs;
type t_array_dct_2d_1_dct_1d_5_mux_flush is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_5_mux_flush: t_array_dct_2d_1_dct_1d_5_mux_flush;
type t_array_dct_2d_1_dct_1d_5_mult_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_5_mult_reg: t_array_dct_2d_1_dct_1d_5_mult_reg;
type t_array_dct_2d_1_dct_1d_5_adder_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_5_adder_reg: t_array_dct_2d_1_dct_1d_5_adder_reg;
type t_array_dct_2d_1_dct_1d_5_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_5_output_sigs: t_array_dct_2d_1_dct_1d_5_output_sigs;
type t_array_dct_2d_1_dct_1d_5_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_5_coeffs: t_array_dct_2d_1_dct_1d_5_coeffs;
type t_array_dct_2d_1_dct_1d_6_mux_flush is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_6_mux_flush: t_array_dct_2d_1_dct_1d_6_mux_flush;
type t_array_dct_2d_1_dct_1d_6_mult_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_6_mult_reg: t_array_dct_2d_1_dct_1d_6_mult_reg;
type t_array_dct_2d_1_dct_1d_6_adder_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_6_adder_reg: t_array_dct_2d_1_dct_1d_6_adder_reg;
type t_array_dct_2d_1_dct_1d_6_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_6_output_sigs: t_array_dct_2d_1_dct_1d_6_output_sigs;
type t_array_dct_2d_1_dct_1d_6_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_6_coeffs: t_array_dct_2d_1_dct_1d_6_coeffs;
type t_array_dct_2d_1_dct_1d_7_mux_flush is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_7_mux_flush: t_array_dct_2d_1_dct_1d_7_mux_flush;
type t_array_dct_2d_1_dct_1d_7_mult_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_7_mult_reg: t_array_dct_2d_1_dct_1d_7_mult_reg;
type t_array_dct_2d_1_dct_1d_7_adder_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_7_adder_reg: t_array_dct_2d_1_dct_1d_7_adder_reg;
type t_array_dct_2d_1_dct_1d_7_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_7_output_sigs: t_array_dct_2d_1_dct_1d_7_output_sigs;
type t_array_dct_2d_1_dct_1d_7_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_7_coeffs: t_array_dct_2d_1_dct_1d_7_coeffs;
type t_array_dct_2d_1_dct_1d_8_mux_flush is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_8_mux_flush: t_array_dct_2d_1_dct_1d_8_mux_flush;
type t_array_dct_2d_1_dct_1d_8_mult_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_8_mult_reg: t_array_dct_2d_1_dct_1d_8_mult_reg;
type t_array_dct_2d_1_dct_1d_8_adder_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_8_adder_reg: t_array_dct_2d_1_dct_1d_8_adder_reg;
type t_array_dct_2d_1_dct_1d_8_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_8_output_sigs: t_array_dct_2d_1_dct_1d_8_output_sigs;
type t_array_dct_2d_1_dct_1d_8_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_8_coeffs: t_array_dct_2d_1_dct_1d_8_coeffs;
type t_array_dct_2d_1_dct_1d_9_mux_flush is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_9_mux_flush: t_array_dct_2d_1_dct_1d_9_mux_flush;
type t_array_dct_2d_1_dct_1d_9_mult_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_9_mult_reg: t_array_dct_2d_1_dct_1d_9_mult_reg;
type t_array_dct_2d_1_dct_1d_9_adder_reg is array(0 to 8-1) of signed (26 downto 0);
signal dct_2d_1_dct_1d_9_adder_reg: t_array_dct_2d_1_dct_1d_9_adder_reg;
type t_array_dct_2d_1_dct_1d_9_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_9_output_sigs: t_array_dct_2d_1_dct_1d_9_output_sigs;
type t_array_dct_2d_1_dct_1d_9_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_9_coeffs: t_array_dct_2d_1_dct_1d_9_coeffs;
type t_array_dct_2d_1_dct_1d_1_mux_flush is array(0 to 8-1) of signed (24 downto 0);
signal dct_2d_1_dct_1d_1_mux_flush: t_array_dct_2d_1_dct_1d_1_mux_flush;
type t_array_dct_2d_1_dct_1d_1_mult_reg is array(0 to 8-1) of signed (24 downto 0);
signal dct_2d_1_dct_1d_1_mult_reg: t_array_dct_2d_1_dct_1d_1_mult_reg;
type t_array_dct_2d_1_dct_1d_1_adder_reg is array(0 to 8-1) of signed (24 downto 0);
signal dct_2d_1_dct_1d_1_adder_reg: t_array_dct_2d_1_dct_1d_1_adder_reg;
type t_array_dct_2d_1_dct_1d_1_output_sigs is array(0 to 8-1) of signed (10 downto 0);
signal dct_2d_1_dct_1d_1_output_sigs: t_array_dct_2d_1_dct_1d_1_output_sigs;
type t_array_dct_2d_1_dct_1d_1_coeffs is array(0 to 8-1) of signed (14 downto 0);
signal dct_2d_1_dct_1d_1_coeffs: t_array_dct_2d_1_dct_1d_1_coeffs;

begin




-- Color Space Equation Conversion Implementation
FRONTEND_TOP_LEVEL_V2_RGB2YCBCR_V2_1_LOGIC: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            rgb2ycbcr_v2_1_color_mode_reg_1 <= to_unsigned(0, 2);
            rgb2ycbcr_v2_1_third_adder_sum <= to_signed(0, 24);
            rgb2ycbcr_out_data_valid <= '0';
            rgb2ycbcr_v2_1_first_adder_sum <= to_signed(0, 24);
            rgb2ycbcr_v2_1_mul_reg(0) <= to_signed(0, 24);
            rgb2ycbcr_v2_1_mul_reg(1) <= to_signed(0, 24);
            rgb2ycbcr_v2_1_mul_reg(2) <= to_signed(0, 24);
            rgb2ycbcr_v2_1_second_adder_sum <= to_signed(0, 24);
            rgb2ycbcr_out_data_out <= to_unsigned(0, 8);
            rgb2ycbcr_v2_1_data_valid_reg(0) <= '0';
            rgb2ycbcr_v2_1_data_valid_reg(1) <= '0';
            rgb2ycbcr_v2_1_data_valid_reg(2) <= '0';
            rgb2ycbcr_v2_1_data_valid_reg(3) <= '0';
            rgb2ycbcr_v2_1_color_mode_reg <= to_unsigned(0, 2);
        else
            rgb2ycbcr_v2_1_mul_reg(0) <= (rgb2ycbcr_v2_1_R_s * rgb2ycbcr_v2_1_coeffs(0));
            rgb2ycbcr_v2_1_mul_reg(1) <= (rgb2ycbcr_v2_1_G_s * rgb2ycbcr_v2_1_coeffs(1));
            rgb2ycbcr_v2_1_mul_reg(2) <= (rgb2ycbcr_v2_1_B_s * rgb2ycbcr_v2_1_coeffs(2));
            rgb2ycbcr_v2_1_color_mode_reg <= inputs_reg_color_mode;
            rgb2ycbcr_v2_1_color_mode_reg_1 <= rgb2ycbcr_v2_1_color_mode_reg;
            rgb2ycbcr_v2_1_first_adder_sum <= (rgb2ycbcr_v2_1_mul_reg_1(0) + rgb2ycbcr_v2_1_mul_reg_1(1));
            rgb2ycbcr_v2_1_second_adder_sum <= (rgb2ycbcr_v2_1_mul_reg_1(2) + rgb2ycbcr_v2_1_offset(to_integer(rgb2ycbcr_v2_1_color_mode_reg_1)));
            rgb2ycbcr_v2_1_third_adder_sum <= (rgb2ycbcr_v2_1_first_adder_sum + rgb2ycbcr_v2_1_second_adder_sum);
            if ((rgb2ycbcr_v2_1_third_adder_sum((14 - 1)) = '1') and (signed(resize(unsigned(rgb2ycbcr_v2_1_third_adder_sum(22-1 downto 14)), 9)) /= (2 ** 8))) then
                rgb2ycbcr_out_data_out <= (unsigned(rgb2ycbcr_v2_1_third_adder_sum(22-1 downto 14)) + 1);
            else
                rgb2ycbcr_out_data_out <= unsigned(rgb2ycbcr_v2_1_third_adder_sum(22-1 downto 14));
            end if;
            rgb2ycbcr_v2_1_data_valid_reg(0) <= inputs_reg_data_valid;
            rgb2ycbcr_v2_1_data_valid_reg(1) <= rgb2ycbcr_v2_1_data_valid_reg(0);
            rgb2ycbcr_v2_1_data_valid_reg(2) <= rgb2ycbcr_v2_1_data_valid_reg(1);
            rgb2ycbcr_v2_1_data_valid_reg(3) <= rgb2ycbcr_v2_1_data_valid_reg(2);
            if bool(inputs_reg_data_valid) then
                rgb2ycbcr_out_data_valid <= rgb2ycbcr_v2_1_data_valid_reg(3);
            else
                rgb2ycbcr_out_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_RGB2YCBCR_V2_1_LOGIC;

-- input RGB to RGB signed

rgb2ycbcr_v2_1_R_s <= signed(resize(inputs_reg_red, 9));
rgb2ycbcr_v2_1_G_s <= signed(resize(inputs_reg_green, 9));
rgb2ycbcr_v2_1_B_s <= signed(resize(inputs_reg_blue, 9));

-- multiplexer for the coefficients
FRONTEND_TOP_LEVEL_V2_RGB2YCBCR_V2_1_COEFF_MUX: process (inputs_reg_color_mode) is
begin
    case inputs_reg_color_mode is
        when "00" =>
            for i in 0 to 3-1 loop
                case i is
                    when 0 => rgb2ycbcr_v2_1_coeffs(i) <= "001001100110010";
                    when 1 => rgb2ycbcr_v2_1_coeffs(i) <= "010010110010001";
                    when others => rgb2ycbcr_v2_1_coeffs(i) <= "000011101001100";
                end case;
            end loop;
        when "01" =>
            for i in 0 to 3-1 loop
                case i is
                    when 0 => rgb2ycbcr_v2_1_coeffs(i) <= "000101011001100";
                    when 1 => rgb2ycbcr_v2_1_coeffs(i) <= "001010100110100";
                    when others => rgb2ycbcr_v2_1_coeffs(i) <= "010000000000000";
                end case;
            end loop;
        when others =>
            for i in 0 to 3-1 loop
                case i is
                    when 0 => rgb2ycbcr_v2_1_coeffs(i) <= "010000000000000";
                    when 1 => rgb2ycbcr_v2_1_coeffs(i) <= "001101011001100";
                    when others => rgb2ycbcr_v2_1_coeffs(i) <= "000010100110100";
                end case;
            end loop;
    end case;
end process FRONTEND_TOP_LEVEL_V2_RGB2YCBCR_V2_1_COEFF_MUX;

-- multiplexer for the sign of the multiplication
FRONTEND_TOP_LEVEL_V2_RGB2YCBCR_V2_1_MUL_REG_SIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            rgb2ycbcr_v2_1_mul_reg_1(0) <= to_signed(0, 24);
            rgb2ycbcr_v2_1_mul_reg_1(1) <= to_signed(0, 24);
            rgb2ycbcr_v2_1_mul_reg_1(2) <= to_signed(0, 24);
        else
            case rgb2ycbcr_v2_1_color_mode_reg is
                when "00" =>
                    rgb2ycbcr_v2_1_mul_reg_1(0) <= rgb2ycbcr_v2_1_mul_reg(0);
                    rgb2ycbcr_v2_1_mul_reg_1(1) <= rgb2ycbcr_v2_1_mul_reg(1);
                    rgb2ycbcr_v2_1_mul_reg_1(2) <= rgb2ycbcr_v2_1_mul_reg(2);
                when "01" =>
                    rgb2ycbcr_v2_1_mul_reg_1(0) <= (-rgb2ycbcr_v2_1_mul_reg(0));
                    rgb2ycbcr_v2_1_mul_reg_1(1) <= (-rgb2ycbcr_v2_1_mul_reg(1));
                    rgb2ycbcr_v2_1_mul_reg_1(2) <= rgb2ycbcr_v2_1_mul_reg(2);
                when others =>
                    rgb2ycbcr_v2_1_mul_reg_1(0) <= rgb2ycbcr_v2_1_mul_reg(0);
                    rgb2ycbcr_v2_1_mul_reg_1(1) <= (-rgb2ycbcr_v2_1_mul_reg(1));
                    rgb2ycbcr_v2_1_mul_reg_1(2) <= (-rgb2ycbcr_v2_1_mul_reg(2));
            end case;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_RGB2YCBCR_V2_1_MUL_REG_SIGN;

FRONTEND_TOP_LEVEL_V2_ZIG_ZAG_1_ZIG_ZAG_ASSIGN: process (clock) is
    variable index: integer;
begin
    if rising_edge(clock) then
        if (reset = '1') then
            zig_zag_out_data_valid <= '0';
            zig_zag_1_output_sigs(0) <= to_signed(0, 11);
            zig_zag_1_output_sigs(1) <= to_signed(0, 11);
            zig_zag_1_output_sigs(2) <= to_signed(0, 11);
            zig_zag_1_output_sigs(3) <= to_signed(0, 11);
            zig_zag_1_output_sigs(4) <= to_signed(0, 11);
            zig_zag_1_output_sigs(5) <= to_signed(0, 11);
            zig_zag_1_output_sigs(6) <= to_signed(0, 11);
            zig_zag_1_output_sigs(7) <= to_signed(0, 11);
            zig_zag_1_output_sigs(8) <= to_signed(0, 11);
            zig_zag_1_output_sigs(9) <= to_signed(0, 11);
            zig_zag_1_output_sigs(10) <= to_signed(0, 11);
            zig_zag_1_output_sigs(11) <= to_signed(0, 11);
            zig_zag_1_output_sigs(12) <= to_signed(0, 11);
            zig_zag_1_output_sigs(13) <= to_signed(0, 11);
            zig_zag_1_output_sigs(14) <= to_signed(0, 11);
            zig_zag_1_output_sigs(15) <= to_signed(0, 11);
            zig_zag_1_output_sigs(16) <= to_signed(0, 11);
            zig_zag_1_output_sigs(17) <= to_signed(0, 11);
            zig_zag_1_output_sigs(18) <= to_signed(0, 11);
            zig_zag_1_output_sigs(19) <= to_signed(0, 11);
            zig_zag_1_output_sigs(20) <= to_signed(0, 11);
            zig_zag_1_output_sigs(21) <= to_signed(0, 11);
            zig_zag_1_output_sigs(22) <= to_signed(0, 11);
            zig_zag_1_output_sigs(23) <= to_signed(0, 11);
            zig_zag_1_output_sigs(24) <= to_signed(0, 11);
            zig_zag_1_output_sigs(25) <= to_signed(0, 11);
            zig_zag_1_output_sigs(26) <= to_signed(0, 11);
            zig_zag_1_output_sigs(27) <= to_signed(0, 11);
            zig_zag_1_output_sigs(28) <= to_signed(0, 11);
            zig_zag_1_output_sigs(29) <= to_signed(0, 11);
            zig_zag_1_output_sigs(30) <= to_signed(0, 11);
            zig_zag_1_output_sigs(31) <= to_signed(0, 11);
            zig_zag_1_output_sigs(32) <= to_signed(0, 11);
            zig_zag_1_output_sigs(33) <= to_signed(0, 11);
            zig_zag_1_output_sigs(34) <= to_signed(0, 11);
            zig_zag_1_output_sigs(35) <= to_signed(0, 11);
            zig_zag_1_output_sigs(36) <= to_signed(0, 11);
            zig_zag_1_output_sigs(37) <= to_signed(0, 11);
            zig_zag_1_output_sigs(38) <= to_signed(0, 11);
            zig_zag_1_output_sigs(39) <= to_signed(0, 11);
            zig_zag_1_output_sigs(40) <= to_signed(0, 11);
            zig_zag_1_output_sigs(41) <= to_signed(0, 11);
            zig_zag_1_output_sigs(42) <= to_signed(0, 11);
            zig_zag_1_output_sigs(43) <= to_signed(0, 11);
            zig_zag_1_output_sigs(44) <= to_signed(0, 11);
            zig_zag_1_output_sigs(45) <= to_signed(0, 11);
            zig_zag_1_output_sigs(46) <= to_signed(0, 11);
            zig_zag_1_output_sigs(47) <= to_signed(0, 11);
            zig_zag_1_output_sigs(48) <= to_signed(0, 11);
            zig_zag_1_output_sigs(49) <= to_signed(0, 11);
            zig_zag_1_output_sigs(50) <= to_signed(0, 11);
            zig_zag_1_output_sigs(51) <= to_signed(0, 11);
            zig_zag_1_output_sigs(52) <= to_signed(0, 11);
            zig_zag_1_output_sigs(53) <= to_signed(0, 11);
            zig_zag_1_output_sigs(54) <= to_signed(0, 11);
            zig_zag_1_output_sigs(55) <= to_signed(0, 11);
            zig_zag_1_output_sigs(56) <= to_signed(0, 11);
            zig_zag_1_output_sigs(57) <= to_signed(0, 11);
            zig_zag_1_output_sigs(58) <= to_signed(0, 11);
            zig_zag_1_output_sigs(59) <= to_signed(0, 11);
            zig_zag_1_output_sigs(60) <= to_signed(0, 11);
            zig_zag_1_output_sigs(61) <= to_signed(0, 11);
            zig_zag_1_output_sigs(62) <= to_signed(0, 11);
            zig_zag_1_output_sigs(63) <= to_signed(0, 11);
        else
            if bool(zig_zag_1_inputs_data_valid) then
                for i in 0 to (8 ** 2)-1 loop
                    case i is
                        when 0 => index := 0;
                        when 1 => index := 1;
                        when 2 => index := 5;
                        when 3 => index := 6;
                        when 4 => index := 14;
                        when 5 => index := 15;
                        when 6 => index := 27;
                        when 7 => index := 28;
                        when 8 => index := 2;
                        when 9 => index := 4;
                        when 10 => index := 7;
                        when 11 => index := 13;
                        when 12 => index := 16;
                        when 13 => index := 26;
                        when 14 => index := 29;
                        when 15 => index := 42;
                        when 16 => index := 3;
                        when 17 => index := 8;
                        when 18 => index := 12;
                        when 19 => index := 17;
                        when 20 => index := 25;
                        when 21 => index := 30;
                        when 22 => index := 41;
                        when 23 => index := 43;
                        when 24 => index := 9;
                        when 25 => index := 11;
                        when 26 => index := 18;
                        when 27 => index := 24;
                        when 28 => index := 31;
                        when 29 => index := 40;
                        when 30 => index := 44;
                        when 31 => index := 53;
                        when 32 => index := 10;
                        when 33 => index := 19;
                        when 34 => index := 23;
                        when 35 => index := 32;
                        when 36 => index := 39;
                        when 37 => index := 45;
                        when 38 => index := 52;
                        when 39 => index := 54;
                        when 40 => index := 20;
                        when 41 => index := 22;
                        when 42 => index := 33;
                        when 43 => index := 38;
                        when 44 => index := 46;
                        when 45 => index := 51;
                        when 46 => index := 55;
                        when 47 => index := 60;
                        when 48 => index := 21;
                        when 49 => index := 34;
                        when 50 => index := 37;
                        when 51 => index := 47;
                        when 52 => index := 50;
                        when 53 => index := 56;
                        when 54 => index := 59;
                        when 55 => index := 61;
                        when 56 => index := 35;
                        when 57 => index := 36;
                        when 58 => index := 48;
                        when 59 => index := 49;
                        when 60 => index := 57;
                        when 61 => index := 58;
                        when 62 => index := 62;
                        when others => index := 63;
                    end case;
                    zig_zag_1_output_sigs(index) <= zig_zag_1_input_sigs(i);
                end loop;
                zig_zag_out_data_valid <= zig_zag_1_inputs_data_valid;
            else
                zig_zag_out_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_ZIG_ZAG_1_ZIG_ZAG_ASSIGN;


zig_zag_out_out_sigs(0) <= zig_zag_1_output_sigs(0);


zig_zag_out_out_sigs(1) <= zig_zag_1_output_sigs(1);


zig_zag_out_out_sigs(2) <= zig_zag_1_output_sigs(2);


zig_zag_out_out_sigs(3) <= zig_zag_1_output_sigs(3);


zig_zag_out_out_sigs(4) <= zig_zag_1_output_sigs(4);


zig_zag_out_out_sigs(5) <= zig_zag_1_output_sigs(5);


zig_zag_out_out_sigs(6) <= zig_zag_1_output_sigs(6);


zig_zag_out_out_sigs(7) <= zig_zag_1_output_sigs(7);


zig_zag_out_out_sigs(8) <= zig_zag_1_output_sigs(8);


zig_zag_out_out_sigs(9) <= zig_zag_1_output_sigs(9);


zig_zag_out_out_sigs(10) <= zig_zag_1_output_sigs(10);


zig_zag_out_out_sigs(11) <= zig_zag_1_output_sigs(11);


zig_zag_out_out_sigs(12) <= zig_zag_1_output_sigs(12);


zig_zag_out_out_sigs(13) <= zig_zag_1_output_sigs(13);


zig_zag_out_out_sigs(14) <= zig_zag_1_output_sigs(14);


zig_zag_out_out_sigs(15) <= zig_zag_1_output_sigs(15);


zig_zag_out_out_sigs(16) <= zig_zag_1_output_sigs(16);


zig_zag_out_out_sigs(17) <= zig_zag_1_output_sigs(17);


zig_zag_out_out_sigs(18) <= zig_zag_1_output_sigs(18);


zig_zag_out_out_sigs(19) <= zig_zag_1_output_sigs(19);


zig_zag_out_out_sigs(20) <= zig_zag_1_output_sigs(20);


zig_zag_out_out_sigs(21) <= zig_zag_1_output_sigs(21);


zig_zag_out_out_sigs(22) <= zig_zag_1_output_sigs(22);


zig_zag_out_out_sigs(23) <= zig_zag_1_output_sigs(23);


zig_zag_out_out_sigs(24) <= zig_zag_1_output_sigs(24);


zig_zag_out_out_sigs(25) <= zig_zag_1_output_sigs(25);


zig_zag_out_out_sigs(26) <= zig_zag_1_output_sigs(26);


zig_zag_out_out_sigs(27) <= zig_zag_1_output_sigs(27);


zig_zag_out_out_sigs(28) <= zig_zag_1_output_sigs(28);


zig_zag_out_out_sigs(29) <= zig_zag_1_output_sigs(29);


zig_zag_out_out_sigs(30) <= zig_zag_1_output_sigs(30);


zig_zag_out_out_sigs(31) <= zig_zag_1_output_sigs(31);


zig_zag_out_out_sigs(32) <= zig_zag_1_output_sigs(32);


zig_zag_out_out_sigs(33) <= zig_zag_1_output_sigs(33);


zig_zag_out_out_sigs(34) <= zig_zag_1_output_sigs(34);


zig_zag_out_out_sigs(35) <= zig_zag_1_output_sigs(35);


zig_zag_out_out_sigs(36) <= zig_zag_1_output_sigs(36);


zig_zag_out_out_sigs(37) <= zig_zag_1_output_sigs(37);


zig_zag_out_out_sigs(38) <= zig_zag_1_output_sigs(38);


zig_zag_out_out_sigs(39) <= zig_zag_1_output_sigs(39);


zig_zag_out_out_sigs(40) <= zig_zag_1_output_sigs(40);


zig_zag_out_out_sigs(41) <= zig_zag_1_output_sigs(41);


zig_zag_out_out_sigs(42) <= zig_zag_1_output_sigs(42);


zig_zag_out_out_sigs(43) <= zig_zag_1_output_sigs(43);


zig_zag_out_out_sigs(44) <= zig_zag_1_output_sigs(44);


zig_zag_out_out_sigs(45) <= zig_zag_1_output_sigs(45);


zig_zag_out_out_sigs(46) <= zig_zag_1_output_sigs(46);


zig_zag_out_out_sigs(47) <= zig_zag_1_output_sigs(47);


zig_zag_out_out_sigs(48) <= zig_zag_1_output_sigs(48);


zig_zag_out_out_sigs(49) <= zig_zag_1_output_sigs(49);


zig_zag_out_out_sigs(50) <= zig_zag_1_output_sigs(50);


zig_zag_out_out_sigs(51) <= zig_zag_1_output_sigs(51);


zig_zag_out_out_sigs(52) <= zig_zag_1_output_sigs(52);


zig_zag_out_out_sigs(53) <= zig_zag_1_output_sigs(53);


zig_zag_out_out_sigs(54) <= zig_zag_1_output_sigs(54);


zig_zag_out_out_sigs(55) <= zig_zag_1_output_sigs(55);


zig_zag_out_out_sigs(56) <= zig_zag_1_output_sigs(56);


zig_zag_out_out_sigs(57) <= zig_zag_1_output_sigs(57);


zig_zag_out_out_sigs(58) <= zig_zag_1_output_sigs(58);


zig_zag_out_out_sigs(59) <= zig_zag_1_output_sigs(59);


zig_zag_out_out_sigs(60) <= zig_zag_1_output_sigs(60);


zig_zag_out_out_sigs(61) <= zig_zag_1_output_sigs(61);


zig_zag_out_out_sigs(62) <= zig_zag_1_output_sigs(62);


zig_zag_out_out_sigs(63) <= zig_zag_1_output_sigs(63);


zig_zag_1_input_sigs(0) <= zig_zag_1_assign_array_11_assign_218_b;


zig_zag_1_input_sigs(1) <= zig_zag_1_assign_array_11_assign_219_b;


zig_zag_1_input_sigs(2) <= zig_zag_1_assign_array_11_assign_220_b;


zig_zag_1_input_sigs(3) <= zig_zag_1_assign_array_11_assign_221_b;


zig_zag_1_input_sigs(4) <= zig_zag_1_assign_array_11_assign_222_b;


zig_zag_1_input_sigs(5) <= zig_zag_1_assign_array_11_assign_223_b;


zig_zag_1_input_sigs(6) <= zig_zag_1_assign_array_11_assign_224_b;


zig_zag_1_input_sigs(7) <= zig_zag_1_assign_array_11_assign_225_b;


zig_zag_1_input_sigs(8) <= zig_zag_1_assign_array_11_assign_226_b;


zig_zag_1_input_sigs(9) <= zig_zag_1_assign_array_11_assign_227_b;


zig_zag_1_input_sigs(10) <= zig_zag_1_assign_array_11_assign_228_b;


zig_zag_1_input_sigs(11) <= zig_zag_1_assign_array_11_assign_229_b;


zig_zag_1_input_sigs(12) <= zig_zag_1_assign_array_11_assign_230_b;


zig_zag_1_input_sigs(13) <= zig_zag_1_assign_array_11_assign_231_b;


zig_zag_1_input_sigs(14) <= zig_zag_1_assign_array_11_assign_232_b;


zig_zag_1_input_sigs(15) <= zig_zag_1_assign_array_11_assign_233_b;


zig_zag_1_input_sigs(16) <= zig_zag_1_assign_array_11_assign_234_b;


zig_zag_1_input_sigs(17) <= zig_zag_1_assign_array_11_assign_235_b;


zig_zag_1_input_sigs(18) <= zig_zag_1_assign_array_11_assign_236_b;


zig_zag_1_input_sigs(19) <= zig_zag_1_assign_array_11_assign_237_b;


zig_zag_1_input_sigs(20) <= zig_zag_1_assign_array_11_assign_238_b;


zig_zag_1_input_sigs(21) <= zig_zag_1_assign_array_11_assign_239_b;


zig_zag_1_input_sigs(22) <= zig_zag_1_assign_array_11_assign_240_b;


zig_zag_1_input_sigs(23) <= zig_zag_1_assign_array_11_assign_241_b;


zig_zag_1_input_sigs(24) <= zig_zag_1_assign_array_11_assign_242_b;


zig_zag_1_input_sigs(25) <= zig_zag_1_assign_array_11_assign_243_b;


zig_zag_1_input_sigs(26) <= zig_zag_1_assign_array_11_assign_244_b;


zig_zag_1_input_sigs(27) <= zig_zag_1_assign_array_11_assign_245_b;


zig_zag_1_input_sigs(28) <= zig_zag_1_assign_array_11_assign_246_b;


zig_zag_1_input_sigs(29) <= zig_zag_1_assign_array_11_assign_247_b;


zig_zag_1_input_sigs(30) <= zig_zag_1_assign_array_11_assign_248_b;


zig_zag_1_input_sigs(31) <= zig_zag_1_assign_array_11_assign_249_b;


zig_zag_1_input_sigs(32) <= zig_zag_1_assign_array_11_assign_250_b;


zig_zag_1_input_sigs(33) <= zig_zag_1_assign_array_11_assign_251_b;


zig_zag_1_input_sigs(34) <= zig_zag_1_assign_array_11_assign_252_b;


zig_zag_1_input_sigs(35) <= zig_zag_1_assign_array_11_assign_253_b;


zig_zag_1_input_sigs(36) <= zig_zag_1_assign_array_11_assign_254_b;


zig_zag_1_input_sigs(37) <= zig_zag_1_assign_array_11_assign_255_b;


zig_zag_1_input_sigs(38) <= zig_zag_1_assign_array_11_assign_256_b;


zig_zag_1_input_sigs(39) <= zig_zag_1_assign_array_11_assign_257_b;


zig_zag_1_input_sigs(40) <= zig_zag_1_assign_array_11_assign_258_b;


zig_zag_1_input_sigs(41) <= zig_zag_1_assign_array_11_assign_259_b;


zig_zag_1_input_sigs(42) <= zig_zag_1_assign_array_11_assign_260_b;


zig_zag_1_input_sigs(43) <= zig_zag_1_assign_array_11_assign_261_b;


zig_zag_1_input_sigs(44) <= zig_zag_1_assign_array_11_assign_262_b;


zig_zag_1_input_sigs(45) <= zig_zag_1_assign_array_11_assign_263_b;


zig_zag_1_input_sigs(46) <= zig_zag_1_assign_array_11_assign_264_b;


zig_zag_1_input_sigs(47) <= zig_zag_1_assign_array_11_assign_265_b;


zig_zag_1_input_sigs(48) <= zig_zag_1_assign_array_11_assign_266_b;


zig_zag_1_input_sigs(49) <= zig_zag_1_assign_array_11_assign_267_b;


zig_zag_1_input_sigs(50) <= zig_zag_1_assign_array_11_assign_268_b;


zig_zag_1_input_sigs(51) <= zig_zag_1_assign_array_11_assign_269_b;


zig_zag_1_input_sigs(52) <= zig_zag_1_assign_array_11_assign_270_b;


zig_zag_1_input_sigs(53) <= zig_zag_1_assign_array_11_assign_271_b;


zig_zag_1_input_sigs(54) <= zig_zag_1_assign_array_11_assign_272_b;


zig_zag_1_input_sigs(55) <= zig_zag_1_assign_array_11_assign_273_b;


zig_zag_1_input_sigs(56) <= zig_zag_1_assign_array_11_assign_274_b;


zig_zag_1_input_sigs(57) <= zig_zag_1_assign_array_11_assign_275_b;


zig_zag_1_input_sigs(58) <= zig_zag_1_assign_array_11_assign_276_b;


zig_zag_1_input_sigs(59) <= zig_zag_1_assign_array_11_assign_277_b;


zig_zag_1_input_sigs(60) <= zig_zag_1_assign_array_11_assign_278_b;


zig_zag_1_input_sigs(61) <= zig_zag_1_assign_array_11_assign_279_b;


zig_zag_1_input_sigs(62) <= zig_zag_1_assign_array_11_assign_280_b;


zig_zag_1_input_sigs(63) <= zig_zag_1_assign_array_11_assign_281_b;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_2_data_in_reg <= to_signed(0, 11);
        else
            if bool(dct_2d_1_dct_1d_2_input_interface_data_valid) then
                dct_2d_1_dct_1d_2_data_in_reg <= dct_2d_1_dct_1d_2_input_interface_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_2_output_interface_data_valid <= '0';
            dct_2d_1_dct_1d_2_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_2_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_2_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_2_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_2_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_2_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_2_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_2_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_2_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_2_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_2_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_2_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_2_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_2_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_dct_1d_2_output_interface_data_valid <= '1';
            else
                dct_2d_1_dct_1d_2_output_interface_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_2_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_2_first_row_passed <= '0';
            dct_2d_1_dct_1d_2_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_dct_1d_2_input_interface_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_2_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_2_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_2_first_row_passed))) then
                    dct_2d_1_dct_1d_2_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_2_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_2_cycles_counter <= (dct_2d_1_dct_1d_2_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_2_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_2_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_2_inputs_counter <= (dct_2d_1_dct_1d_2_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_2_adder_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_adder_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_adder_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_adder_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_adder_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_adder_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_adder_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_adder_reg(7) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_mult_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_mult_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_mult_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_mult_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_mult_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_mult_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_mult_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_2_mult_reg(7) <= to_signed(0, 27);
        else
            if bool(dct_2d_1_dct_1d_2_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_2_mult_reg(i) <= (resize(dct_2d_1_dct_1d_2_data_in_reg, 12) * dct_2d_1_dct_1d_2_coeffs(i));
                    dct_2d_1_dct_1d_2_adder_reg(i) <= (dct_2d_1_dct_1d_2_mux_flush(i) + dct_2d_1_dct_1d_2_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_2_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_2_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_2_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_2_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_2_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_2_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_2_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_2_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_dct_1d_2_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_2_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_2_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_2_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_2_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_2_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_2_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_2_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_2_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_2_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_2_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_2_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_2_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_2_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_2_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_2_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_2_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_2_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_2_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_2_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_2_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_2_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_2_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_2_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_2_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_2_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_2_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_2_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_2_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_2_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_2_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_2_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_2_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_2_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_2_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_2_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_2_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_2_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_2_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_2_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_2_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_2_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_2_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_2_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_2_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_2_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_2_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_2_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_2_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_2_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_2_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_2_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_2_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_2_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_2_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_2_cycles_counter, dct_2d_1_dct_1d_2_first_row_passed, dct_2d_1_dct_1d_2_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_2_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_2_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_2_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_2_mux_flush(i) <= to_signed(0, 27);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_2_mux_flush(i) <= dct_2d_1_dct_1d_2_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_2_MUX_AFTER_ADDER_REG;


dct_2d_1_dct_1d_2_assign_array_2_assign_9_a <= dct_2d_1_dct_1d_2_output_sigs(0);


dct_2d_1_dct_1d_2_assign_array_2_assign_10_a <= dct_2d_1_dct_1d_2_output_sigs(1);


dct_2d_1_dct_1d_2_assign_array_2_assign_11_a <= dct_2d_1_dct_1d_2_output_sigs(2);


dct_2d_1_dct_1d_2_assign_array_2_assign_12_a <= dct_2d_1_dct_1d_2_output_sigs(3);


dct_2d_1_dct_1d_2_assign_array_2_assign_13_a <= dct_2d_1_dct_1d_2_output_sigs(4);


dct_2d_1_dct_1d_2_assign_array_2_assign_14_a <= dct_2d_1_dct_1d_2_output_sigs(5);


dct_2d_1_dct_1d_2_assign_array_2_assign_15_a <= dct_2d_1_dct_1d_2_output_sigs(6);


dct_2d_1_dct_1d_2_assign_array_2_assign_16_a <= dct_2d_1_dct_1d_2_output_sigs(7);


dct_2d_1_dct_1d_2_input_interface_data_in <= dct_2d_1_assign_17_b;


dct_2d_1_dct_1d_2_input_interface_data_valid <= dct_2d_1_assign_18_b;


zig_zag_1_assign_array_11_assign_218_b <= dct_2d_1_dct_1d_2_assign_array_2_assign_9_a;


zig_zag_1_assign_array_11_assign_226_b <= dct_2d_1_dct_1d_2_assign_array_2_assign_10_a;


zig_zag_1_assign_array_11_assign_234_b <= dct_2d_1_dct_1d_2_assign_array_2_assign_11_a;


zig_zag_1_assign_array_11_assign_242_b <= dct_2d_1_dct_1d_2_assign_array_2_assign_12_a;


zig_zag_1_assign_array_11_assign_250_b <= dct_2d_1_dct_1d_2_assign_array_2_assign_13_a;


zig_zag_1_assign_array_11_assign_258_b <= dct_2d_1_dct_1d_2_assign_array_2_assign_14_a;


zig_zag_1_assign_array_11_assign_266_b <= dct_2d_1_dct_1d_2_assign_array_2_assign_15_a;


zig_zag_1_assign_array_11_assign_274_b <= dct_2d_1_dct_1d_2_assign_array_2_assign_16_a;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_3_data_in_reg <= to_signed(0, 11);
        else
            if bool(dct_2d_1_dct_1d_3_input_interface_data_valid) then
                dct_2d_1_dct_1d_3_data_in_reg <= dct_2d_1_dct_1d_3_input_interface_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_3_output_interface_data_valid <= '0';
            dct_2d_1_dct_1d_3_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_3_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_3_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_3_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_3_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_3_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_3_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_3_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_3_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_3_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_3_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_3_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_3_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_3_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_dct_1d_3_output_interface_data_valid <= '1';
            else
                dct_2d_1_dct_1d_3_output_interface_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_3_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_3_first_row_passed <= '0';
            dct_2d_1_dct_1d_3_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_dct_1d_3_input_interface_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_3_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_3_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_3_first_row_passed))) then
                    dct_2d_1_dct_1d_3_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_3_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_3_cycles_counter <= (dct_2d_1_dct_1d_3_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_3_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_3_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_3_inputs_counter <= (dct_2d_1_dct_1d_3_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_3_adder_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_adder_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_adder_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_adder_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_adder_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_adder_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_adder_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_adder_reg(7) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_mult_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_mult_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_mult_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_mult_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_mult_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_mult_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_mult_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_3_mult_reg(7) <= to_signed(0, 27);
        else
            if bool(dct_2d_1_dct_1d_3_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_3_mult_reg(i) <= (resize(dct_2d_1_dct_1d_3_data_in_reg, 12) * dct_2d_1_dct_1d_3_coeffs(i));
                    dct_2d_1_dct_1d_3_adder_reg(i) <= (dct_2d_1_dct_1d_3_mux_flush(i) + dct_2d_1_dct_1d_3_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_3_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_3_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_3_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_3_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_3_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_3_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_3_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_3_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_dct_1d_3_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_3_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_3_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_3_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_3_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_3_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_3_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_3_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_3_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_3_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_3_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_3_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_3_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_3_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_3_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_3_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_3_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_3_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_3_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_3_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_3_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_3_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_3_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_3_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_3_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_3_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_3_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_3_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_3_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_3_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_3_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_3_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_3_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_3_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_3_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_3_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_3_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_3_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_3_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_3_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_3_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_3_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_3_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_3_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_3_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_3_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_3_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_3_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_3_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_3_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_3_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_3_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_3_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_3_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_3_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_3_cycles_counter, dct_2d_1_dct_1d_3_first_row_passed, dct_2d_1_dct_1d_3_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_3_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_3_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_3_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_3_mux_flush(i) <= to_signed(0, 27);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_3_mux_flush(i) <= dct_2d_1_dct_1d_3_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_3_MUX_AFTER_ADDER_REG;


dct_2d_1_dct_1d_3_assign_array_3_assign_27_a <= dct_2d_1_dct_1d_3_output_sigs(0);


dct_2d_1_dct_1d_3_assign_array_3_assign_28_a <= dct_2d_1_dct_1d_3_output_sigs(1);


dct_2d_1_dct_1d_3_assign_array_3_assign_29_a <= dct_2d_1_dct_1d_3_output_sigs(2);


dct_2d_1_dct_1d_3_assign_array_3_assign_30_a <= dct_2d_1_dct_1d_3_output_sigs(3);


dct_2d_1_dct_1d_3_assign_array_3_assign_31_a <= dct_2d_1_dct_1d_3_output_sigs(4);


dct_2d_1_dct_1d_3_assign_array_3_assign_32_a <= dct_2d_1_dct_1d_3_output_sigs(5);


dct_2d_1_dct_1d_3_assign_array_3_assign_33_a <= dct_2d_1_dct_1d_3_output_sigs(6);


dct_2d_1_dct_1d_3_assign_array_3_assign_34_a <= dct_2d_1_dct_1d_3_output_sigs(7);


dct_2d_1_dct_1d_3_input_interface_data_in <= dct_2d_1_assign_35_b;


dct_2d_1_dct_1d_3_input_interface_data_valid <= dct_2d_1_assign_18_b;


zig_zag_1_assign_array_11_assign_219_b <= dct_2d_1_dct_1d_3_assign_array_3_assign_27_a;


zig_zag_1_assign_array_11_assign_227_b <= dct_2d_1_dct_1d_3_assign_array_3_assign_28_a;


zig_zag_1_assign_array_11_assign_235_b <= dct_2d_1_dct_1d_3_assign_array_3_assign_29_a;


zig_zag_1_assign_array_11_assign_243_b <= dct_2d_1_dct_1d_3_assign_array_3_assign_30_a;


zig_zag_1_assign_array_11_assign_251_b <= dct_2d_1_dct_1d_3_assign_array_3_assign_31_a;


zig_zag_1_assign_array_11_assign_259_b <= dct_2d_1_dct_1d_3_assign_array_3_assign_32_a;


zig_zag_1_assign_array_11_assign_267_b <= dct_2d_1_dct_1d_3_assign_array_3_assign_33_a;


zig_zag_1_assign_array_11_assign_275_b <= dct_2d_1_dct_1d_3_assign_array_3_assign_34_a;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_4_data_in_reg <= to_signed(0, 11);
        else
            if bool(dct_2d_1_dct_1d_4_input_interface_data_valid) then
                dct_2d_1_dct_1d_4_data_in_reg <= dct_2d_1_dct_1d_4_input_interface_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_4_output_interface_data_valid <= '0';
            dct_2d_1_dct_1d_4_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_4_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_4_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_4_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_4_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_4_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_4_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_4_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_4_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_4_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_4_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_4_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_4_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_4_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_dct_1d_4_output_interface_data_valid <= '1';
            else
                dct_2d_1_dct_1d_4_output_interface_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_4_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_4_first_row_passed <= '0';
            dct_2d_1_dct_1d_4_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_dct_1d_4_input_interface_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_4_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_4_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_4_first_row_passed))) then
                    dct_2d_1_dct_1d_4_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_4_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_4_cycles_counter <= (dct_2d_1_dct_1d_4_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_4_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_4_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_4_inputs_counter <= (dct_2d_1_dct_1d_4_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_4_adder_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_adder_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_adder_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_adder_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_adder_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_adder_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_adder_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_adder_reg(7) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_mult_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_mult_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_mult_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_mult_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_mult_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_mult_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_mult_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_4_mult_reg(7) <= to_signed(0, 27);
        else
            if bool(dct_2d_1_dct_1d_4_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_4_mult_reg(i) <= (resize(dct_2d_1_dct_1d_4_data_in_reg, 12) * dct_2d_1_dct_1d_4_coeffs(i));
                    dct_2d_1_dct_1d_4_adder_reg(i) <= (dct_2d_1_dct_1d_4_mux_flush(i) + dct_2d_1_dct_1d_4_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_4_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_4_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_4_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_4_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_4_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_4_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_4_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_4_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_dct_1d_4_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_4_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_4_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_4_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_4_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_4_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_4_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_4_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_4_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_4_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_4_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_4_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_4_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_4_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_4_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_4_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_4_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_4_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_4_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_4_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_4_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_4_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_4_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_4_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_4_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_4_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_4_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_4_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_4_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_4_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_4_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_4_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_4_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_4_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_4_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_4_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_4_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_4_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_4_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_4_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_4_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_4_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_4_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_4_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_4_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_4_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_4_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_4_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_4_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_4_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_4_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_4_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_4_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_4_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_4_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_4_cycles_counter, dct_2d_1_dct_1d_4_first_row_passed, dct_2d_1_dct_1d_4_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_4_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_4_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_4_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_4_mux_flush(i) <= to_signed(0, 27);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_4_mux_flush(i) <= dct_2d_1_dct_1d_4_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_4_MUX_AFTER_ADDER_REG;


dct_2d_1_dct_1d_4_assign_array_4_assign_45_a <= dct_2d_1_dct_1d_4_output_sigs(0);


dct_2d_1_dct_1d_4_assign_array_4_assign_46_a <= dct_2d_1_dct_1d_4_output_sigs(1);


dct_2d_1_dct_1d_4_assign_array_4_assign_47_a <= dct_2d_1_dct_1d_4_output_sigs(2);


dct_2d_1_dct_1d_4_assign_array_4_assign_48_a <= dct_2d_1_dct_1d_4_output_sigs(3);


dct_2d_1_dct_1d_4_assign_array_4_assign_49_a <= dct_2d_1_dct_1d_4_output_sigs(4);


dct_2d_1_dct_1d_4_assign_array_4_assign_50_a <= dct_2d_1_dct_1d_4_output_sigs(5);


dct_2d_1_dct_1d_4_assign_array_4_assign_51_a <= dct_2d_1_dct_1d_4_output_sigs(6);


dct_2d_1_dct_1d_4_assign_array_4_assign_52_a <= dct_2d_1_dct_1d_4_output_sigs(7);


dct_2d_1_dct_1d_4_input_interface_data_in <= dct_2d_1_assign_53_b;


dct_2d_1_dct_1d_4_input_interface_data_valid <= dct_2d_1_assign_18_b;


zig_zag_1_assign_array_11_assign_220_b <= dct_2d_1_dct_1d_4_assign_array_4_assign_45_a;


zig_zag_1_assign_array_11_assign_228_b <= dct_2d_1_dct_1d_4_assign_array_4_assign_46_a;


zig_zag_1_assign_array_11_assign_236_b <= dct_2d_1_dct_1d_4_assign_array_4_assign_47_a;


zig_zag_1_assign_array_11_assign_244_b <= dct_2d_1_dct_1d_4_assign_array_4_assign_48_a;


zig_zag_1_assign_array_11_assign_252_b <= dct_2d_1_dct_1d_4_assign_array_4_assign_49_a;


zig_zag_1_assign_array_11_assign_260_b <= dct_2d_1_dct_1d_4_assign_array_4_assign_50_a;


zig_zag_1_assign_array_11_assign_268_b <= dct_2d_1_dct_1d_4_assign_array_4_assign_51_a;


zig_zag_1_assign_array_11_assign_276_b <= dct_2d_1_dct_1d_4_assign_array_4_assign_52_a;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_5_data_in_reg <= to_signed(0, 11);
        else
            if bool(dct_2d_1_dct_1d_5_input_interface_data_valid) then
                dct_2d_1_dct_1d_5_data_in_reg <= dct_2d_1_dct_1d_5_input_interface_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_5_output_interface_data_valid <= '0';
            dct_2d_1_dct_1d_5_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_5_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_5_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_5_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_5_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_5_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_5_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_5_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_5_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_5_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_5_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_5_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_5_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_5_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_dct_1d_5_output_interface_data_valid <= '1';
            else
                dct_2d_1_dct_1d_5_output_interface_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_5_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_5_first_row_passed <= '0';
            dct_2d_1_dct_1d_5_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_dct_1d_5_input_interface_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_5_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_5_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_5_first_row_passed))) then
                    dct_2d_1_dct_1d_5_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_5_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_5_cycles_counter <= (dct_2d_1_dct_1d_5_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_5_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_5_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_5_inputs_counter <= (dct_2d_1_dct_1d_5_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_5_adder_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_adder_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_adder_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_adder_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_adder_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_adder_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_adder_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_adder_reg(7) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_mult_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_mult_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_mult_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_mult_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_mult_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_mult_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_mult_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_5_mult_reg(7) <= to_signed(0, 27);
        else
            if bool(dct_2d_1_dct_1d_5_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_5_mult_reg(i) <= (resize(dct_2d_1_dct_1d_5_data_in_reg, 12) * dct_2d_1_dct_1d_5_coeffs(i));
                    dct_2d_1_dct_1d_5_adder_reg(i) <= (dct_2d_1_dct_1d_5_mux_flush(i) + dct_2d_1_dct_1d_5_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_5_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_5_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_5_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_5_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_5_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_5_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_5_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_5_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_dct_1d_5_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_5_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_5_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_5_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_5_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_5_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_5_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_5_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_5_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_5_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_5_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_5_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_5_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_5_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_5_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_5_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_5_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_5_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_5_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_5_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_5_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_5_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_5_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_5_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_5_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_5_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_5_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_5_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_5_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_5_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_5_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_5_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_5_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_5_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_5_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_5_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_5_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_5_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_5_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_5_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_5_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_5_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_5_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_5_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_5_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_5_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_5_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_5_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_5_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_5_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_5_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_5_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_5_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_5_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_5_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_5_cycles_counter, dct_2d_1_dct_1d_5_first_row_passed, dct_2d_1_dct_1d_5_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_5_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_5_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_5_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_5_mux_flush(i) <= to_signed(0, 27);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_5_mux_flush(i) <= dct_2d_1_dct_1d_5_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_5_MUX_AFTER_ADDER_REG;


dct_2d_1_dct_1d_5_assign_array_5_assign_63_a <= dct_2d_1_dct_1d_5_output_sigs(0);


dct_2d_1_dct_1d_5_assign_array_5_assign_64_a <= dct_2d_1_dct_1d_5_output_sigs(1);


dct_2d_1_dct_1d_5_assign_array_5_assign_65_a <= dct_2d_1_dct_1d_5_output_sigs(2);


dct_2d_1_dct_1d_5_assign_array_5_assign_66_a <= dct_2d_1_dct_1d_5_output_sigs(3);


dct_2d_1_dct_1d_5_assign_array_5_assign_67_a <= dct_2d_1_dct_1d_5_output_sigs(4);


dct_2d_1_dct_1d_5_assign_array_5_assign_68_a <= dct_2d_1_dct_1d_5_output_sigs(5);


dct_2d_1_dct_1d_5_assign_array_5_assign_69_a <= dct_2d_1_dct_1d_5_output_sigs(6);


dct_2d_1_dct_1d_5_assign_array_5_assign_70_a <= dct_2d_1_dct_1d_5_output_sigs(7);


dct_2d_1_dct_1d_5_input_interface_data_in <= dct_2d_1_assign_71_b;


dct_2d_1_dct_1d_5_input_interface_data_valid <= dct_2d_1_assign_18_b;


zig_zag_1_assign_array_11_assign_221_b <= dct_2d_1_dct_1d_5_assign_array_5_assign_63_a;


zig_zag_1_assign_array_11_assign_229_b <= dct_2d_1_dct_1d_5_assign_array_5_assign_64_a;


zig_zag_1_assign_array_11_assign_237_b <= dct_2d_1_dct_1d_5_assign_array_5_assign_65_a;


zig_zag_1_assign_array_11_assign_245_b <= dct_2d_1_dct_1d_5_assign_array_5_assign_66_a;


zig_zag_1_assign_array_11_assign_253_b <= dct_2d_1_dct_1d_5_assign_array_5_assign_67_a;


zig_zag_1_assign_array_11_assign_261_b <= dct_2d_1_dct_1d_5_assign_array_5_assign_68_a;


zig_zag_1_assign_array_11_assign_269_b <= dct_2d_1_dct_1d_5_assign_array_5_assign_69_a;


zig_zag_1_assign_array_11_assign_277_b <= dct_2d_1_dct_1d_5_assign_array_5_assign_70_a;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_6_data_in_reg <= to_signed(0, 11);
        else
            if bool(dct_2d_1_dct_1d_6_input_interface_data_valid) then
                dct_2d_1_dct_1d_6_data_in_reg <= dct_2d_1_dct_1d_6_input_interface_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_6_output_interface_data_valid <= '0';
            dct_2d_1_dct_1d_6_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_6_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_6_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_6_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_6_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_6_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_6_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_6_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_6_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_6_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_6_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_6_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_6_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_6_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_dct_1d_6_output_interface_data_valid <= '1';
            else
                dct_2d_1_dct_1d_6_output_interface_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_6_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_6_first_row_passed <= '0';
            dct_2d_1_dct_1d_6_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_dct_1d_6_input_interface_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_6_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_6_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_6_first_row_passed))) then
                    dct_2d_1_dct_1d_6_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_6_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_6_cycles_counter <= (dct_2d_1_dct_1d_6_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_6_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_6_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_6_inputs_counter <= (dct_2d_1_dct_1d_6_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_6_adder_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_adder_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_adder_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_adder_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_adder_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_adder_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_adder_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_adder_reg(7) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_mult_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_mult_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_mult_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_mult_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_mult_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_mult_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_mult_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_6_mult_reg(7) <= to_signed(0, 27);
        else
            if bool(dct_2d_1_dct_1d_6_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_6_mult_reg(i) <= (resize(dct_2d_1_dct_1d_6_data_in_reg, 12) * dct_2d_1_dct_1d_6_coeffs(i));
                    dct_2d_1_dct_1d_6_adder_reg(i) <= (dct_2d_1_dct_1d_6_mux_flush(i) + dct_2d_1_dct_1d_6_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_6_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_6_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_6_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_6_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_6_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_6_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_6_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_6_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_dct_1d_6_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_6_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_6_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_6_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_6_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_6_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_6_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_6_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_6_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_6_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_6_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_6_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_6_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_6_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_6_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_6_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_6_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_6_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_6_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_6_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_6_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_6_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_6_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_6_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_6_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_6_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_6_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_6_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_6_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_6_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_6_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_6_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_6_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_6_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_6_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_6_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_6_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_6_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_6_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_6_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_6_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_6_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_6_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_6_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_6_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_6_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_6_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_6_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_6_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_6_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_6_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_6_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_6_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_6_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_6_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_6_cycles_counter, dct_2d_1_dct_1d_6_first_row_passed, dct_2d_1_dct_1d_6_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_6_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_6_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_6_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_6_mux_flush(i) <= to_signed(0, 27);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_6_mux_flush(i) <= dct_2d_1_dct_1d_6_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_6_MUX_AFTER_ADDER_REG;


dct_2d_1_dct_1d_6_assign_array_6_assign_81_a <= dct_2d_1_dct_1d_6_output_sigs(0);


dct_2d_1_dct_1d_6_assign_array_6_assign_82_a <= dct_2d_1_dct_1d_6_output_sigs(1);


dct_2d_1_dct_1d_6_assign_array_6_assign_83_a <= dct_2d_1_dct_1d_6_output_sigs(2);


dct_2d_1_dct_1d_6_assign_array_6_assign_84_a <= dct_2d_1_dct_1d_6_output_sigs(3);


dct_2d_1_dct_1d_6_assign_array_6_assign_85_a <= dct_2d_1_dct_1d_6_output_sigs(4);


dct_2d_1_dct_1d_6_assign_array_6_assign_86_a <= dct_2d_1_dct_1d_6_output_sigs(5);


dct_2d_1_dct_1d_6_assign_array_6_assign_87_a <= dct_2d_1_dct_1d_6_output_sigs(6);


dct_2d_1_dct_1d_6_assign_array_6_assign_88_a <= dct_2d_1_dct_1d_6_output_sigs(7);


dct_2d_1_dct_1d_6_input_interface_data_in <= dct_2d_1_assign_89_b;


dct_2d_1_dct_1d_6_input_interface_data_valid <= dct_2d_1_assign_18_b;


zig_zag_1_assign_array_11_assign_222_b <= dct_2d_1_dct_1d_6_assign_array_6_assign_81_a;


zig_zag_1_assign_array_11_assign_230_b <= dct_2d_1_dct_1d_6_assign_array_6_assign_82_a;


zig_zag_1_assign_array_11_assign_238_b <= dct_2d_1_dct_1d_6_assign_array_6_assign_83_a;


zig_zag_1_assign_array_11_assign_246_b <= dct_2d_1_dct_1d_6_assign_array_6_assign_84_a;


zig_zag_1_assign_array_11_assign_254_b <= dct_2d_1_dct_1d_6_assign_array_6_assign_85_a;


zig_zag_1_assign_array_11_assign_262_b <= dct_2d_1_dct_1d_6_assign_array_6_assign_86_a;


zig_zag_1_assign_array_11_assign_270_b <= dct_2d_1_dct_1d_6_assign_array_6_assign_87_a;


zig_zag_1_assign_array_11_assign_278_b <= dct_2d_1_dct_1d_6_assign_array_6_assign_88_a;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_7_data_in_reg <= to_signed(0, 11);
        else
            if bool(dct_2d_1_dct_1d_7_input_interface_data_valid) then
                dct_2d_1_dct_1d_7_data_in_reg <= dct_2d_1_dct_1d_7_input_interface_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_7_output_interface_data_valid <= '0';
            dct_2d_1_dct_1d_7_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_7_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_7_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_7_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_7_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_7_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_7_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_7_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_7_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_7_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_7_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_7_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_7_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_7_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_dct_1d_7_output_interface_data_valid <= '1';
            else
                dct_2d_1_dct_1d_7_output_interface_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_7_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_7_first_row_passed <= '0';
            dct_2d_1_dct_1d_7_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_dct_1d_7_input_interface_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_7_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_7_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_7_first_row_passed))) then
                    dct_2d_1_dct_1d_7_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_7_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_7_cycles_counter <= (dct_2d_1_dct_1d_7_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_7_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_7_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_7_inputs_counter <= (dct_2d_1_dct_1d_7_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_7_adder_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_adder_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_adder_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_adder_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_adder_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_adder_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_adder_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_adder_reg(7) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_mult_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_mult_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_mult_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_mult_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_mult_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_mult_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_mult_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_7_mult_reg(7) <= to_signed(0, 27);
        else
            if bool(dct_2d_1_dct_1d_7_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_7_mult_reg(i) <= (resize(dct_2d_1_dct_1d_7_data_in_reg, 12) * dct_2d_1_dct_1d_7_coeffs(i));
                    dct_2d_1_dct_1d_7_adder_reg(i) <= (dct_2d_1_dct_1d_7_mux_flush(i) + dct_2d_1_dct_1d_7_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_7_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_7_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_7_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_7_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_7_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_7_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_7_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_7_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_dct_1d_7_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_7_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_7_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_7_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_7_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_7_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_7_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_7_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_7_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_7_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_7_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_7_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_7_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_7_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_7_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_7_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_7_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_7_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_7_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_7_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_7_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_7_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_7_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_7_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_7_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_7_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_7_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_7_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_7_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_7_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_7_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_7_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_7_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_7_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_7_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_7_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_7_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_7_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_7_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_7_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_7_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_7_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_7_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_7_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_7_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_7_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_7_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_7_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_7_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_7_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_7_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_7_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_7_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_7_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_7_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_7_cycles_counter, dct_2d_1_dct_1d_7_first_row_passed, dct_2d_1_dct_1d_7_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_7_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_7_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_7_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_7_mux_flush(i) <= to_signed(0, 27);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_7_mux_flush(i) <= dct_2d_1_dct_1d_7_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_7_MUX_AFTER_ADDER_REG;


dct_2d_1_dct_1d_7_assign_array_7_assign_99_a <= dct_2d_1_dct_1d_7_output_sigs(0);


dct_2d_1_dct_1d_7_assign_array_7_assign_100_a <= dct_2d_1_dct_1d_7_output_sigs(1);


dct_2d_1_dct_1d_7_assign_array_7_assign_101_a <= dct_2d_1_dct_1d_7_output_sigs(2);


dct_2d_1_dct_1d_7_assign_array_7_assign_102_a <= dct_2d_1_dct_1d_7_output_sigs(3);


dct_2d_1_dct_1d_7_assign_array_7_assign_103_a <= dct_2d_1_dct_1d_7_output_sigs(4);


dct_2d_1_dct_1d_7_assign_array_7_assign_104_a <= dct_2d_1_dct_1d_7_output_sigs(5);


dct_2d_1_dct_1d_7_assign_array_7_assign_105_a <= dct_2d_1_dct_1d_7_output_sigs(6);


dct_2d_1_dct_1d_7_assign_array_7_assign_106_a <= dct_2d_1_dct_1d_7_output_sigs(7);


dct_2d_1_dct_1d_7_input_interface_data_in <= dct_2d_1_assign_107_b;


dct_2d_1_dct_1d_7_input_interface_data_valid <= dct_2d_1_assign_18_b;


zig_zag_1_assign_array_11_assign_223_b <= dct_2d_1_dct_1d_7_assign_array_7_assign_99_a;


zig_zag_1_assign_array_11_assign_231_b <= dct_2d_1_dct_1d_7_assign_array_7_assign_100_a;


zig_zag_1_assign_array_11_assign_239_b <= dct_2d_1_dct_1d_7_assign_array_7_assign_101_a;


zig_zag_1_assign_array_11_assign_247_b <= dct_2d_1_dct_1d_7_assign_array_7_assign_102_a;


zig_zag_1_assign_array_11_assign_255_b <= dct_2d_1_dct_1d_7_assign_array_7_assign_103_a;


zig_zag_1_assign_array_11_assign_263_b <= dct_2d_1_dct_1d_7_assign_array_7_assign_104_a;


zig_zag_1_assign_array_11_assign_271_b <= dct_2d_1_dct_1d_7_assign_array_7_assign_105_a;


zig_zag_1_assign_array_11_assign_279_b <= dct_2d_1_dct_1d_7_assign_array_7_assign_106_a;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_8_data_in_reg <= to_signed(0, 11);
        else
            if bool(dct_2d_1_dct_1d_8_input_interface_data_valid) then
                dct_2d_1_dct_1d_8_data_in_reg <= dct_2d_1_dct_1d_8_input_interface_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_8_output_interface_data_valid <= '0';
            dct_2d_1_dct_1d_8_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_8_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_8_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_8_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_8_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_8_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_8_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_8_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_8_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_8_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_8_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_8_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_8_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_8_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_dct_1d_8_output_interface_data_valid <= '1';
            else
                dct_2d_1_dct_1d_8_output_interface_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_8_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_8_first_row_passed <= '0';
            dct_2d_1_dct_1d_8_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_dct_1d_8_input_interface_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_8_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_8_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_8_first_row_passed))) then
                    dct_2d_1_dct_1d_8_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_8_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_8_cycles_counter <= (dct_2d_1_dct_1d_8_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_8_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_8_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_8_inputs_counter <= (dct_2d_1_dct_1d_8_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_8_adder_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_adder_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_adder_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_adder_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_adder_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_adder_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_adder_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_adder_reg(7) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_mult_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_mult_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_mult_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_mult_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_mult_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_mult_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_mult_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_8_mult_reg(7) <= to_signed(0, 27);
        else
            if bool(dct_2d_1_dct_1d_8_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_8_mult_reg(i) <= (resize(dct_2d_1_dct_1d_8_data_in_reg, 12) * dct_2d_1_dct_1d_8_coeffs(i));
                    dct_2d_1_dct_1d_8_adder_reg(i) <= (dct_2d_1_dct_1d_8_mux_flush(i) + dct_2d_1_dct_1d_8_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_8_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_8_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_8_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_8_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_8_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_8_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_8_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_8_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_dct_1d_8_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_8_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_8_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_8_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_8_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_8_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_8_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_8_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_8_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_8_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_8_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_8_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_8_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_8_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_8_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_8_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_8_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_8_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_8_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_8_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_8_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_8_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_8_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_8_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_8_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_8_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_8_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_8_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_8_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_8_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_8_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_8_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_8_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_8_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_8_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_8_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_8_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_8_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_8_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_8_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_8_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_8_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_8_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_8_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_8_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_8_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_8_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_8_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_8_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_8_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_8_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_8_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_8_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_8_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_8_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_8_cycles_counter, dct_2d_1_dct_1d_8_first_row_passed, dct_2d_1_dct_1d_8_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_8_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_8_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_8_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_8_mux_flush(i) <= to_signed(0, 27);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_8_mux_flush(i) <= dct_2d_1_dct_1d_8_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_8_MUX_AFTER_ADDER_REG;


dct_2d_1_dct_1d_8_assign_array_8_assign_117_a <= dct_2d_1_dct_1d_8_output_sigs(0);


dct_2d_1_dct_1d_8_assign_array_8_assign_118_a <= dct_2d_1_dct_1d_8_output_sigs(1);


dct_2d_1_dct_1d_8_assign_array_8_assign_119_a <= dct_2d_1_dct_1d_8_output_sigs(2);


dct_2d_1_dct_1d_8_assign_array_8_assign_120_a <= dct_2d_1_dct_1d_8_output_sigs(3);


dct_2d_1_dct_1d_8_assign_array_8_assign_121_a <= dct_2d_1_dct_1d_8_output_sigs(4);


dct_2d_1_dct_1d_8_assign_array_8_assign_122_a <= dct_2d_1_dct_1d_8_output_sigs(5);


dct_2d_1_dct_1d_8_assign_array_8_assign_123_a <= dct_2d_1_dct_1d_8_output_sigs(6);


dct_2d_1_dct_1d_8_assign_array_8_assign_124_a <= dct_2d_1_dct_1d_8_output_sigs(7);


dct_2d_1_dct_1d_8_input_interface_data_in <= dct_2d_1_assign_125_b;


dct_2d_1_dct_1d_8_input_interface_data_valid <= dct_2d_1_assign_18_b;


zig_zag_1_assign_array_11_assign_224_b <= dct_2d_1_dct_1d_8_assign_array_8_assign_117_a;


zig_zag_1_assign_array_11_assign_232_b <= dct_2d_1_dct_1d_8_assign_array_8_assign_118_a;


zig_zag_1_assign_array_11_assign_240_b <= dct_2d_1_dct_1d_8_assign_array_8_assign_119_a;


zig_zag_1_assign_array_11_assign_248_b <= dct_2d_1_dct_1d_8_assign_array_8_assign_120_a;


zig_zag_1_assign_array_11_assign_256_b <= dct_2d_1_dct_1d_8_assign_array_8_assign_121_a;


zig_zag_1_assign_array_11_assign_264_b <= dct_2d_1_dct_1d_8_assign_array_8_assign_122_a;


zig_zag_1_assign_array_11_assign_272_b <= dct_2d_1_dct_1d_8_assign_array_8_assign_123_a;


zig_zag_1_assign_array_11_assign_280_b <= dct_2d_1_dct_1d_8_assign_array_8_assign_124_a;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_9_data_in_reg <= to_signed(0, 11);
        else
            if bool(dct_2d_1_dct_1d_9_input_interface_data_valid) then
                dct_2d_1_dct_1d_9_data_in_reg <= dct_2d_1_dct_1d_9_input_interface_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_9_output_interface_data_valid <= '0';
            dct_2d_1_dct_1d_9_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_9_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_9_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_9_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_9_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_9_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_9_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_9_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_9_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_9_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_9_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_9_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_9_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_9_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_dct_1d_9_output_interface_data_valid <= '1';
            else
                dct_2d_1_dct_1d_9_output_interface_data_valid <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_9_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_9_first_row_passed <= '0';
            dct_2d_1_dct_1d_9_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_dct_1d_9_input_interface_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_9_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_9_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_9_first_row_passed))) then
                    dct_2d_1_dct_1d_9_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_9_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_9_cycles_counter <= (dct_2d_1_dct_1d_9_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_9_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_9_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_9_inputs_counter <= (dct_2d_1_dct_1d_9_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_9_adder_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_adder_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_adder_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_adder_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_adder_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_adder_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_adder_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_adder_reg(7) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_mult_reg(0) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_mult_reg(1) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_mult_reg(2) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_mult_reg(3) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_mult_reg(4) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_mult_reg(5) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_mult_reg(6) <= to_signed(0, 27);
            dct_2d_1_dct_1d_9_mult_reg(7) <= to_signed(0, 27);
        else
            if bool(dct_2d_1_dct_1d_9_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_9_mult_reg(i) <= (resize(dct_2d_1_dct_1d_9_data_in_reg, 12) * dct_2d_1_dct_1d_9_coeffs(i));
                    dct_2d_1_dct_1d_9_adder_reg(i) <= (dct_2d_1_dct_1d_9_mux_flush(i) + dct_2d_1_dct_1d_9_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_9_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_9_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_9_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_9_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_9_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_9_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_9_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_9_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_dct_1d_9_input_interface_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_9_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_9_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_9_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_9_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_9_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_9_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_9_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_9_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_9_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_9_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_9_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_9_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_9_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_9_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_9_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_9_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_9_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_9_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_9_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_9_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_9_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_9_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_9_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_9_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_9_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_9_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_9_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_9_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_9_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_9_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_9_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_9_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_9_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_9_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_9_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_9_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_9_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_9_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_9_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_9_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_9_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_9_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_9_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_9_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_9_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_9_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_9_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_9_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_9_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_9_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_9_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_9_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_9_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_9_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_9_cycles_counter, dct_2d_1_dct_1d_9_first_row_passed, dct_2d_1_dct_1d_9_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_9_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_9_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_9_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_9_mux_flush(i) <= to_signed(0, 27);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_9_mux_flush(i) <= dct_2d_1_dct_1d_9_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_9_MUX_AFTER_ADDER_REG;


dct_2d_1_dct_1d_9_assign_array_9_assign_135_a <= dct_2d_1_dct_1d_9_output_sigs(0);


dct_2d_1_dct_1d_9_assign_array_9_assign_136_a <= dct_2d_1_dct_1d_9_output_sigs(1);


dct_2d_1_dct_1d_9_assign_array_9_assign_137_a <= dct_2d_1_dct_1d_9_output_sigs(2);


dct_2d_1_dct_1d_9_assign_array_9_assign_138_a <= dct_2d_1_dct_1d_9_output_sigs(3);


dct_2d_1_dct_1d_9_assign_array_9_assign_139_a <= dct_2d_1_dct_1d_9_output_sigs(4);


dct_2d_1_dct_1d_9_assign_array_9_assign_140_a <= dct_2d_1_dct_1d_9_output_sigs(5);


dct_2d_1_dct_1d_9_assign_array_9_assign_141_a <= dct_2d_1_dct_1d_9_output_sigs(6);


dct_2d_1_dct_1d_9_assign_array_9_assign_142_a <= dct_2d_1_dct_1d_9_output_sigs(7);


dct_2d_1_dct_1d_9_input_interface_data_in <= dct_2d_1_assign_143_b;


dct_2d_1_dct_1d_9_input_interface_data_valid <= dct_2d_1_assign_18_b;


zig_zag_1_assign_array_11_assign_225_b <= dct_2d_1_dct_1d_9_assign_array_9_assign_135_a;


zig_zag_1_assign_array_11_assign_233_b <= dct_2d_1_dct_1d_9_assign_array_9_assign_136_a;


zig_zag_1_assign_array_11_assign_241_b <= dct_2d_1_dct_1d_9_assign_array_9_assign_137_a;


zig_zag_1_assign_array_11_assign_249_b <= dct_2d_1_dct_1d_9_assign_array_9_assign_138_a;


zig_zag_1_assign_array_11_assign_257_b <= dct_2d_1_dct_1d_9_assign_array_9_assign_139_a;


zig_zag_1_assign_array_11_assign_265_b <= dct_2d_1_dct_1d_9_assign_array_9_assign_140_a;


zig_zag_1_assign_array_11_assign_273_b <= dct_2d_1_dct_1d_9_assign_array_9_assign_141_a;


zig_zag_1_assign_array_11_assign_281_b <= dct_2d_1_dct_1d_9_assign_array_9_assign_142_a;


dct_2d_1_outputs_data_valid <= dct_2d_1_dct_1d_2_output_interface_data_valid;

-- Align to zero each input
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_INPUT_SUBTRACT: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_data_in_signed <= to_signed(0, 9);
            dct_2d_1_input_1d_stage_1_data_valid <= '0';
            dct_2d_1_data_valid_reg <= '0';
            dct_2d_1_input_1d_stage_1_data_in <= to_signed(0, 9);
        else
            if bool(dct_2d_input_data_valid) then
                dct_2d_1_data_in_signed <= signed(resize(dct_2d_input_data_in, 9));
                dct_2d_1_input_1d_stage_1_data_in <= (dct_2d_1_data_in_signed - 128);
                dct_2d_1_data_valid_reg <= dct_2d_input_data_valid;
                dct_2d_1_input_1d_stage_1_data_valid <= dct_2d_1_data_valid_reg;
            else
                dct_2d_1_data_in_signed <= to_signed(0, 9);
                dct_2d_1_input_1d_stage_1_data_in <= dct_2d_1_data_in_signed;
                dct_2d_1_data_valid_reg <= '0';
                dct_2d_1_input_1d_stage_1_data_valid <= dct_2d_1_data_valid_reg;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_INPUT_SUBTRACT;


zig_zag_1_inputs_data_valid <= dct_2d_1_data_valid_reg2;

-- Counter update
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_COUNTER_UPDATE: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_outputs_data_valid) then
                if (signed(resize(dct_2d_1_counter, 4)) = (8 - 1)) then
                    dct_2d_1_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_counter <= (dct_2d_1_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_COUNTER_UPDATE;

-- Data valid signal assignment when the outputs are valid
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DATA_VALID_2D: process (dct_2d_1_outputs_data_valid, dct_2d_1_counter) is
begin
    if (bool(dct_2d_1_outputs_data_valid) and (dct_2d_1_counter = 0)) then
        dct_2d_1_data_valid_reg2 <= '1';
    else
        dct_2d_1_data_valid_reg2 <= '0';
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DATA_VALID_2D;

-- input register
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_1_data_in_reg <= to_signed(0, 9);
        else
            if bool(dct_2d_1_input_1d_stage_1_data_valid) then
                dct_2d_1_dct_1d_1_data_in_reg <= dct_2d_1_input_1d_stage_1_data_in;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_INPUT_REG;

-- rounding
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_OUTPUTS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_assign_18_b <= '0';
            dct_2d_1_dct_1d_1_output_sigs(0) <= to_signed(0, 11);
            dct_2d_1_dct_1d_1_output_sigs(1) <= to_signed(0, 11);
            dct_2d_1_dct_1d_1_output_sigs(2) <= to_signed(0, 11);
            dct_2d_1_dct_1d_1_output_sigs(3) <= to_signed(0, 11);
            dct_2d_1_dct_1d_1_output_sigs(4) <= to_signed(0, 11);
            dct_2d_1_dct_1d_1_output_sigs(5) <= to_signed(0, 11);
            dct_2d_1_dct_1d_1_output_sigs(6) <= to_signed(0, 11);
            dct_2d_1_dct_1d_1_output_sigs(7) <= to_signed(0, 11);
        else
            for i in 0 to 8-1 loop
                dct_2d_1_dct_1d_1_output_sigs(i) <= (signed(unsigned(dct_2d_1_dct_1d_1_adder_reg(i)(25-1 downto 14))) + to_signed(dct_2d_1_dct_1d_1_adder_reg(i)(13), 2));
            end loop;
            if ((signed(resize(dct_2d_1_dct_1d_1_cycles_counter, 5)) = (8 + 2)) or (bool(dct_2d_1_dct_1d_1_first_row_passed) and (signed(resize(dct_2d_1_dct_1d_1_cycles_counter, 5)) = (8 - 1)))) then
                dct_2d_1_assign_18_b <= '1';
            else
                dct_2d_1_assign_18_b <= '0';
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_OUTPUTS;

-- inputs and cycles counter
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_COUNTERS: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_1_cycles_counter <= to_unsigned(0, 4);
            dct_2d_1_dct_1d_1_first_row_passed <= '0';
            dct_2d_1_dct_1d_1_inputs_counter <= to_unsigned(0, 3);
        else
            if bool(dct_2d_1_input_1d_stage_1_data_valid) then
                if ((signed(resize(dct_2d_1_dct_1d_1_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_1_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_1_first_row_passed))) then
                    dct_2d_1_dct_1d_1_cycles_counter <= to_unsigned(0, 4);
                    dct_2d_1_dct_1d_1_first_row_passed <= '1';
                else
                    dct_2d_1_dct_1d_1_cycles_counter <= (dct_2d_1_dct_1d_1_cycles_counter + 1);
                end if;
                if (signed(resize(dct_2d_1_dct_1d_1_inputs_counter, 4)) = (8 - 1)) then
                    dct_2d_1_dct_1d_1_inputs_counter <= to_unsigned(0, 3);
                else
                    dct_2d_1_dct_1d_1_inputs_counter <= (dct_2d_1_dct_1d_1_inputs_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_COUNTERS;

-- multiplication and addition
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_MUL_ADD: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_1_adder_reg(0) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_adder_reg(1) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_adder_reg(2) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_adder_reg(3) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_adder_reg(4) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_adder_reg(5) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_adder_reg(6) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_adder_reg(7) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_mult_reg(0) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_mult_reg(1) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_mult_reg(2) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_mult_reg(3) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_mult_reg(4) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_mult_reg(5) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_mult_reg(6) <= to_signed(0, 25);
            dct_2d_1_dct_1d_1_mult_reg(7) <= to_signed(0, 25);
        else
            if bool(dct_2d_1_input_1d_stage_1_data_valid) then
                for i in 0 to 8-1 loop
                    dct_2d_1_dct_1d_1_mult_reg(i) <= (resize(dct_2d_1_dct_1d_1_data_in_reg, 10) * dct_2d_1_dct_1d_1_coeffs(i));
                    dct_2d_1_dct_1d_1_adder_reg(i) <= (dct_2d_1_dct_1d_1_mux_flush(i) + dct_2d_1_dct_1d_1_mult_reg(i));
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_MUL_ADD;

-- coefficient assignment from rom
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_COEFF_ASSIGN: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_1_dct_1d_1_coeffs(0) <= to_signed(0, 15);
            dct_2d_1_dct_1d_1_coeffs(1) <= to_signed(0, 15);
            dct_2d_1_dct_1d_1_coeffs(2) <= to_signed(0, 15);
            dct_2d_1_dct_1d_1_coeffs(3) <= to_signed(0, 15);
            dct_2d_1_dct_1d_1_coeffs(4) <= to_signed(0, 15);
            dct_2d_1_dct_1d_1_coeffs(5) <= to_signed(0, 15);
            dct_2d_1_dct_1d_1_coeffs(6) <= to_signed(0, 15);
            dct_2d_1_dct_1d_1_coeffs(7) <= to_signed(0, 15);
        else
            if bool(dct_2d_1_input_1d_stage_1_data_valid) then
                for i in 0 to 8-1 loop
                    case ((i * 8) + to_integer(dct_2d_1_dct_1d_1_inputs_counter)) is
                        when 0 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 1 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 2 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 3 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 4 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 5 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 6 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 7 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 8 => dct_2d_1_dct_1d_1_coeffs(i) <= "001111101100011";
                        when 9 => dct_2d_1_dct_1d_1_coeffs(i) <= "001101010011011";
                        when 10 => dct_2d_1_dct_1d_1_coeffs(i) <= "001000111000111";
                        when 11 => dct_2d_1_dct_1d_1_coeffs(i) <= "000011000111110";
                        when 12 => dct_2d_1_dct_1d_1_coeffs(i) <= "111100111000010";
                        when 13 => dct_2d_1_dct_1d_1_coeffs(i) <= "110111000111001";
                        when 14 => dct_2d_1_dct_1d_1_coeffs(i) <= "110010101100101";
                        when 15 => dct_2d_1_dct_1d_1_coeffs(i) <= "110000010011101";
                        when 16 => dct_2d_1_dct_1d_1_coeffs(i) <= "001110110010000";
                        when 17 => dct_2d_1_dct_1d_1_coeffs(i) <= "000110000111111";
                        when 18 => dct_2d_1_dct_1d_1_coeffs(i) <= "111001111000001";
                        when 19 => dct_2d_1_dct_1d_1_coeffs(i) <= "110001001110000";
                        when 20 => dct_2d_1_dct_1d_1_coeffs(i) <= "110001001110000";
                        when 21 => dct_2d_1_dct_1d_1_coeffs(i) <= "111001111000001";
                        when 22 => dct_2d_1_dct_1d_1_coeffs(i) <= "000110000111111";
                        when 23 => dct_2d_1_dct_1d_1_coeffs(i) <= "001110110010000";
                        when 24 => dct_2d_1_dct_1d_1_coeffs(i) <= "001101010011011";
                        when 25 => dct_2d_1_dct_1d_1_coeffs(i) <= "111100111000010";
                        when 26 => dct_2d_1_dct_1d_1_coeffs(i) <= "110000010011101";
                        when 27 => dct_2d_1_dct_1d_1_coeffs(i) <= "110111000111001";
                        when 28 => dct_2d_1_dct_1d_1_coeffs(i) <= "001000111000111";
                        when 29 => dct_2d_1_dct_1d_1_coeffs(i) <= "001111101100011";
                        when 30 => dct_2d_1_dct_1d_1_coeffs(i) <= "000011000111110";
                        when 31 => dct_2d_1_dct_1d_1_coeffs(i) <= "110010101100101";
                        when 32 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 33 => dct_2d_1_dct_1d_1_coeffs(i) <= "110100101011111";
                        when 34 => dct_2d_1_dct_1d_1_coeffs(i) <= "110100101011111";
                        when 35 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 36 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 37 => dct_2d_1_dct_1d_1_coeffs(i) <= "110100101011111";
                        when 38 => dct_2d_1_dct_1d_1_coeffs(i) <= "110100101011111";
                        when 39 => dct_2d_1_dct_1d_1_coeffs(i) <= "001011010100001";
                        when 40 => dct_2d_1_dct_1d_1_coeffs(i) <= "001000111000111";
                        when 41 => dct_2d_1_dct_1d_1_coeffs(i) <= "110000010011101";
                        when 42 => dct_2d_1_dct_1d_1_coeffs(i) <= "000011000111110";
                        when 43 => dct_2d_1_dct_1d_1_coeffs(i) <= "001101010011011";
                        when 44 => dct_2d_1_dct_1d_1_coeffs(i) <= "110010101100101";
                        when 45 => dct_2d_1_dct_1d_1_coeffs(i) <= "111100111000010";
                        when 46 => dct_2d_1_dct_1d_1_coeffs(i) <= "001111101100011";
                        when 47 => dct_2d_1_dct_1d_1_coeffs(i) <= "110111000111001";
                        when 48 => dct_2d_1_dct_1d_1_coeffs(i) <= "000110000111111";
                        when 49 => dct_2d_1_dct_1d_1_coeffs(i) <= "110001001110000";
                        when 50 => dct_2d_1_dct_1d_1_coeffs(i) <= "001110110010000";
                        when 51 => dct_2d_1_dct_1d_1_coeffs(i) <= "111001111000001";
                        when 52 => dct_2d_1_dct_1d_1_coeffs(i) <= "111001111000001";
                        when 53 => dct_2d_1_dct_1d_1_coeffs(i) <= "001110110010000";
                        when 54 => dct_2d_1_dct_1d_1_coeffs(i) <= "110001001110000";
                        when 55 => dct_2d_1_dct_1d_1_coeffs(i) <= "000110000111111";
                        when 56 => dct_2d_1_dct_1d_1_coeffs(i) <= "000011000111110";
                        when 57 => dct_2d_1_dct_1d_1_coeffs(i) <= "110111000111001";
                        when 58 => dct_2d_1_dct_1d_1_coeffs(i) <= "001101010011011";
                        when 59 => dct_2d_1_dct_1d_1_coeffs(i) <= "110000010011101";
                        when 60 => dct_2d_1_dct_1d_1_coeffs(i) <= "001111101100011";
                        when 61 => dct_2d_1_dct_1d_1_coeffs(i) <= "110010101100101";
                        when 62 => dct_2d_1_dct_1d_1_coeffs(i) <= "001000111000111";
                        when others => dct_2d_1_dct_1d_1_coeffs(i) <= "111100111000010";
                    end case;
                end loop;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_COEFF_ASSIGN;

-- after 8 inputs flush one of the inputs of the adder
FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_MUX_AFTER_ADDER_REG: process (dct_2d_1_dct_1d_1_cycles_counter, dct_2d_1_dct_1d_1_first_row_passed, dct_2d_1_dct_1d_1_adder_reg) is
begin
    if ((signed(resize(dct_2d_1_dct_1d_1_cycles_counter, 5)) = (8 + 2)) or ((signed(resize(dct_2d_1_dct_1d_1_cycles_counter, 5)) = (8 - 1)) and bool(dct_2d_1_dct_1d_1_first_row_passed))) then
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_1_mux_flush(i) <= to_signed(0, 25);
        end loop;
    else
        for i in 0 to 8-1 loop
            dct_2d_1_dct_1d_1_mux_flush(i) <= dct_2d_1_dct_1d_1_adder_reg(i);
        end loop;
    end if;
end process FRONTEND_TOP_LEVEL_V2_DCT_2D_1_DCT_1D_1_MUX_AFTER_ADDER_REG;


dct_2d_1_assign_17_b <= dct_2d_1_dct_1d_1_output_sigs(0);


dct_2d_1_assign_35_b <= dct_2d_1_dct_1d_1_output_sigs(1);


dct_2d_1_assign_53_b <= dct_2d_1_dct_1d_1_output_sigs(2);


dct_2d_1_assign_71_b <= dct_2d_1_dct_1d_1_output_sigs(3);


dct_2d_1_assign_89_b <= dct_2d_1_dct_1d_1_output_sigs(4);


dct_2d_1_assign_107_b <= dct_2d_1_dct_1d_1_output_sigs(5);


dct_2d_1_assign_125_b <= dct_2d_1_dct_1d_1_output_sigs(6);


dct_2d_1_assign_143_b <= dct_2d_1_dct_1d_1_output_sigs(7);

-- signal assignment from color_space_conversion module to dct_2d inputs
FRONTEND_TOP_LEVEL_V2_COLOR_SPACE_TO_DCT: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            dct_2d_input_data_in <= to_unsigned(0, 8);
            dct_2d_input_data_valid <= '0';
        else
            if bool(rgb2ycbcr_out_data_valid) then
                dct_2d_input_data_in <= rgb2ycbcr_out_data_out;
                dct_2d_input_data_valid <= rgb2ycbcr_out_data_valid;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_COLOR_SPACE_TO_DCT;

-- signal assignment from zig zag to output
FRONTEND_TOP_LEVEL_V2_ZIG_ZAG_TO_OUTPUT_MUX: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            outputs_data_out <= to_signed(0, 11);
        else
            if bool(start_out) then
                outputs_data_out <= zig_zag_out_out_sigs(to_integer(output_counter));
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_ZIG_ZAG_TO_OUTPUT_MUX;

-- Is used to update the control signal color_mode for the first mux of the rgb2ycbcr
-- output to 2d dct
FRONTEND_TOP_LEVEL_V2_FIRST_CONTROL_SIGNALS_UPDATE: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            input_counter <= to_unsigned(0, 6);
            color_mode <= to_unsigned(0, 2);
        else
            if bool(inputs_data_valid) then
                if (input_counter = 63) then
                    input_counter <= to_unsigned(0, 6);
                    if (color_mode = 2) then
                        color_mode <= to_unsigned(0, 2);
                    else
                        color_mode <= (color_mode + 1);
                    end if;
                else
                    input_counter <= (input_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_FIRST_CONTROL_SIGNALS_UPDATE;

FRONTEND_TOP_LEVEL_V2_SET_START_OUT: process (zig_zag_out_data_valid) is
begin
    if bool(zig_zag_out_data_valid) then
        start_out <= '1';
        outputs_data_valid <= zig_zag_out_data_valid;
    else
        outputs_data_valid <= '0';
    end if;
end process FRONTEND_TOP_LEVEL_V2_SET_START_OUT;

FRONTEND_TOP_LEVEL_V2_OUTPUT_COUNTER_RESET: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            output_counter <= to_unsigned(0, 6);
        else
            if bool(start_out) then
                if (output_counter = 63) then
                    output_counter <= to_unsigned(0, 6);
                else
                    output_counter <= (output_counter + 1);
                end if;
            end if;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_OUTPUT_COUNTER_RESET;

FRONTEND_TOP_LEVEL_V2_INPUT_REG: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            inputs_reg_color_mode <= to_unsigned(0, 2);
            inputs_reg_red <= to_unsigned(0, 8);
            inputs_reg_blue <= to_unsigned(0, 8);
            inputs_reg_data_valid <= '0';
            inputs_reg_green <= to_unsigned(0, 8);
        else
            inputs_reg_red <= inputs_red;
            inputs_reg_green <= inputs_green;
            inputs_reg_blue <= inputs_blue;
            inputs_reg_data_valid <= inputs_data_valid;
            inputs_reg_color_mode <= color_mode;
        end if;
    end if;
end process FRONTEND_TOP_LEVEL_V2_INPUT_REG;

end architecture MyHDL;