bug.py

#!/usr/bin/env python
# coding=utf-8


from myhdl import *
from myhdl.conversion import *
from random import randrange

const = [-2, -3]

@block
def negative_assignment(a, b):

    #bug
    s1 = Signal(intbv(const[0], min=-10, max=10))
    s2 = Signal(intbv(const[1], min=-10, max=10))

    s3 = Signal(intbv(0, min=-100, max=100))
    s4=Signal(intbv(0,min=-2**33,max=2**33))

    @always_comb
    def logic():

        s3.next = s1+s2

        b.next = a

    return logic


def convert():

    a, b = [Signal(bool(0)) for _ in range(2)]
    instance = negative_assignment(a, b)
    instance.convert(hdl='verilog')

    # analysis of converted code
    analyze.simulator = 'iverilog'
    assert negative_assignment(a, b).analyze_convert == 0

if __name__ == '__main__':
    convert()

generated verilog code

// File: negative_assignment.v
// Generated by MyHDL 1.0dev
// Date: Thu May 26 17:54:25 2016


`timescale 1ns/10ps

module negative_assignment (
    a,
    b
);


input a;
output b;
wire b;

wire signed [7:0] s3;
wire [4:0] s2;
wire [4:0] s1;


assign s2 = 5'd-3;
assign s1 = 5'd-2;




assign s3 = (s1 + s2);
assign b = a;

endmodule