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1)N=bits pou prepei na athroisw kai input to shma mou | |
2) exw ena component enan adder me inputs:a,b kai output:c=====> adder(a,b,c) | |
3) exw array apo signals gia na ta exw ekei gia na ginei swsta to port map. kanw assign ekei ta outputs ton adders. | |
este oti to leme out array. epishs to megethos tou einai N-1 kai exei ta outputs twn endiameswn adders. esy tha oriseis to bitwidth. | |
gia n>4 | |
for i in 0 to log2(N) - 2: | |
for j in 0 to N/2 - 2*i - 1: | |
if i==0 generate: | |
adder(input(2*j),input(2*j+1),out(j)) | |
else generate: | |
adder(out((i-1)*N/2 +j), out ((i-1)*N/2 +1 +j), out(i*N/2 + j)) | |
adder(out(N - 4),out(N -3),out(N-2)) | |
exeis to teliko apotelesma sthn thesh out(N-2) | |
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