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July 24, 2016 13:03
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| #----------------------------------------------------------- | |
| # Vivado v2014.4 (64-bit) | |
| # SW Build 1071353 on Tue Nov 18 18:29:27 MST 2014 | |
| # IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 | |
| # Start of session at: Sat Jul 23 10:57:45 2016 | |
| # Process ID: 400 | |
| # Log file: C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.runs/synth_1/frontend_top_level_v2.vds | |
| # Journal file: C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.runs/synth_1\vivado.jou | |
| #----------------------------------------------------------- | |
| source frontend_top_level_v2.tcl | |
| # set_param general.maxThreads 8 | |
| # set_param gui.test TreeTableDev | |
| # debug::add_scope template.lib 1 | |
| # set_msg_config -id {HDL 9-1061} -limit 100000 | |
| # set_msg_config -id {HDL 9-1654} -limit 100000 | |
| # set_msg_config -id {Synth 8-256} -limit 10000 | |
| # set_msg_config -id {Synth 8-638} -limit 10000 | |
| # create_project -in_memory -part xc7vx690tffg1761-2 | |
| # set_param project.compositeFile.enableAutoGeneration 0 | |
| # set_param synth.vivado.isSynthRun true | |
| # set_property webtalk.parent_dir C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.cache/wt [current_project] | |
| # set_property parent.project_path C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.xpr [current_project] | |
| # set_property default_lib xil_defaultlib [current_project] | |
| # set_property target_language VHDL [current_project] | |
| # read_vhdl -library xil_defaultlib { | |
| # C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/pck_myhdl_10.vhd | |
| # C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd | |
| # } | |
| # read_xdc C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/constrs_1/imports/merk/constraint.xdc | |
| # set_property used_in_implementation false [get_files C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/constrs_1/imports/merk/constraint.xdc] | |
| # catch { write_hwdef -file frontend_top_level_v2.hwdef } | |
| INFO: [Vivado_Tcl 4-279] hardware handoff file cannot be generated as there is no block diagram instance in the design | |
| # synth_design -top frontend_top_level_v2 -part xc7vx690tffg1761-2 | |
| Command: synth_design -top frontend_top_level_v2 -part xc7vx690tffg1761-2 | |
| Starting synth_design | |
| Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx690t' | |
| INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx690t' | |
| INFO: [Common 17-1223] The version limit for your license is '2014.12' and will expire in -570 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. | |
| --------------------------------------------------------------------------------- | |
| Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 247.383 ; gain = 48.809 | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-638] synthesizing module 'frontend_top_level_v2' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:30] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000001000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000001001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000001010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000001011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000001100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000001101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000001110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000001111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000010111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000011111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000100111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000101111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110101 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110110 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000110111 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111000 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111001 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111010 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111011 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| WARNING: [Synth 8-153] case item 31'b0000000000000000000000000111100 will never be executed [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| INFO: [Common 17-14] Message 'Synth 8-153' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1098] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1353] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1353] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1353] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1353] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1608] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1608] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1608] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1608] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1863] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1863] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1863] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1863] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2118] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2118] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2118] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2118] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2373] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2373] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2373] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2373] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2628] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2628] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2628] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2628] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2883] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2883] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2883] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2883] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3192] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3192] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3192] | |
| INFO: [Synth 8-226] default block is never used [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3192] | |
| Warning: Trying to implement RAM in registers. Block RAM or DRAM implementation is not possible for one or more of the following reasons : | |
| 1: Unable to determine number of words or word size in RAM. | |
| RAM dissolved into registers | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_mul_reg_1[0] in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:268] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_mul_reg_1[1] in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:268] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_mul_reg_1[2] in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:268] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_offset in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:262] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_offset in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:262] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_offset in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:262] | |
| INFO: [Synth 8-256] done synthesizing module 'frontend_top_level_v2' (1#1) [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:30] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port outputs_end_of_block_conversion | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_color_mode[1] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_color_mode[0] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[7] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[6] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[5] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[4] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[3] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[2] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[1] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[0] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[7] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[6] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[5] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[4] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[3] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[2] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[1] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[0] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[7] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[6] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[5] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[4] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[3] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[2] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[1] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[0] | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 298.309 ; gain = 99.734 | |
| --------------------------------------------------------------------------------- | |
| Report Check Netlist: | |
| +------+------------------+-------+---------+-------+------------------+ | |
| | |Item |Errors |Warnings |Status |Description | | |
| +------+------------------+-------+---------+-------+------------------+ | |
| |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | | |
| +------+------------------+-------+---------+-------+------------------+ | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 298.309 ; gain = 99.734 | |
| --------------------------------------------------------------------------------- | |
| Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/virtex7/virtex7/xc7vx690t/ClockRegion.xml | |
| Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/virtex7/virtex7/xc7vx690t/ClockBuffers.xml | |
| Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/virtex7/ClockPlacerRules.xml | |
| Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/virtex7/PinFunctions.xml... | |
| Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/virtex7/virtex7/xc7vx690t/ffg1761/Package.xml | |
| Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/virtex7/IOStandards.xml | |
| Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/virtex7/ConfigModes.xml | |
| INFO: [Project 1-570] Preparing netlist for logic optimization | |
| Processing XDC Constraints | |
| Initializing timing engine | |
| Parsing XDC File [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/constrs_1/imports/merk/constraint.xdc] | |
| Finished Parsing XDC File [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/constrs_1/imports/merk/constraint.xdc] | |
| Completed Processing XDC Constraints | |
| INFO: [Project 1-111] Unisim Transformation Summary: | |
| No Unisim elements were transformed. | |
| Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 809.703 ; gain = 0.000 | |
| --------------------------------------------------------------------------------- | |
| Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Loading Part and Timing Information | |
| --------------------------------------------------------------------------------- | |
| Loading part: xc7vx690tffg1761-2 | |
| --------------------------------------------------------------------------------- | |
| Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Applying 'set_property' XDC Constraints | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_3_coeffs_reg[0][14:0]' into 'dct_2d_1_dct_1d_2_coeffs_reg[0][14:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1329] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_4_coeffs_reg[0][14:0]' into 'dct_2d_1_dct_1d_2_coeffs_reg[0][14:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1584] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_5_coeffs_reg[0][14:0]' into 'dct_2d_1_dct_1d_2_coeffs_reg[0][14:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1839] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_6_coeffs_reg[0][14:0]' into 'dct_2d_1_dct_1d_2_coeffs_reg[0][14:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2094] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_7_coeffs_reg[0][14:0]' into 'dct_2d_1_dct_1d_2_coeffs_reg[0][14:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2349] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_8_coeffs_reg[0][14:0]' into 'dct_2d_1_dct_1d_2_coeffs_reg[0][14:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2604] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_9_coeffs_reg[0][14:0]' into 'dct_2d_1_dct_1d_2_coeffs_reg[0][14:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2859] | |
| ROM "color_mode" won't be mapped to RAM because it is too sparse. | |
| WARNING: [Synth 8-327] inferring latch for variable 'start_out_reg' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3318] | |
| WARNING: [Synth 8-327] inferring latch for variable 'dct_2d_input_data_valid_reg' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3036] | |
| WARNING: [Synth 8-327] inferring latch for variable 'dct_2d_input_data_in_reg' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3037] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_offset in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:262] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_offset in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:262] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_offset in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:262] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_mul_reg_1[2] in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:268] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_mul_reg_1[1] in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:268] | |
| WARNING: [Synth 8-3848] Net rgb2ycbcr_v2_1_mul_reg_1[0] in module/entity frontend_top_level_v2 does not have driver. [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:268] | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start RTL Component Statistics | |
| --------------------------------------------------------------------------------- | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 24 Bit Adders := 3 | |
| 2 Input 11 Bit Adders := 72 | |
| 2 Input 9 Bit Adders := 1 | |
| 2 Input 8 Bit Adders := 1 | |
| 2 Input 6 Bit Adders := 2 | |
| 2 Input 4 Bit Adders := 9 | |
| 2 Input 3 Bit Adders := 10 | |
| 2 Input 2 Bit Adders := 1 | |
| +---Registers : | |
| 24 Bit Registers := 3 | |
| 15 Bit Registers := 47 | |
| 11 Bit Registers := 153 | |
| 9 Bit Registers := 4 | |
| 8 Bit Registers := 1 | |
| 6 Bit Registers := 2 | |
| 4 Bit Registers := 9 | |
| 3 Bit Registers := 11 | |
| 2 Bit Registers := 3 | |
| 1 Bit Registers := 15 | |
| +---Muxes : | |
| 2 Input 27 Bit Muxes := 64 | |
| 2 Input 25 Bit Muxes := 8 | |
| 3 Input 24 Bit Muxes := 1 | |
| 2 Input 15 Bit Muxes := 4 | |
| 16 Input 15 Bit Muxes := 9 | |
| 2 Input 9 Bit Muxes := 2 | |
| 2 Input 6 Bit Muxes := 2 | |
| 2 Input 3 Bit Muxes := 10 | |
| 2 Input 2 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 12 | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Component Statistics | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start RTL Hierarchical Component Statistics | |
| --------------------------------------------------------------------------------- | |
| Hierarchical RTL Component report | |
| Module frontend_top_level_v2 | |
| Detailed RTL Component Info : | |
| +---Adders : | |
| 2 Input 24 Bit Adders := 3 | |
| 2 Input 11 Bit Adders := 72 | |
| 2 Input 9 Bit Adders := 1 | |
| 2 Input 8 Bit Adders := 1 | |
| 2 Input 6 Bit Adders := 2 | |
| 2 Input 4 Bit Adders := 9 | |
| 2 Input 3 Bit Adders := 10 | |
| 2 Input 2 Bit Adders := 1 | |
| +---Registers : | |
| 24 Bit Registers := 3 | |
| 15 Bit Registers := 47 | |
| 11 Bit Registers := 153 | |
| 9 Bit Registers := 4 | |
| 8 Bit Registers := 1 | |
| 6 Bit Registers := 2 | |
| 4 Bit Registers := 9 | |
| 3 Bit Registers := 11 | |
| 2 Bit Registers := 3 | |
| 1 Bit Registers := 15 | |
| +---Muxes : | |
| 2 Input 27 Bit Muxes := 64 | |
| 2 Input 25 Bit Muxes := 8 | |
| 3 Input 24 Bit Muxes := 1 | |
| 2 Input 15 Bit Muxes := 4 | |
| 16 Input 15 Bit Muxes := 9 | |
| 2 Input 9 Bit Muxes := 2 | |
| 2 Input 6 Bit Muxes := 2 | |
| 2 Input 3 Bit Muxes := 10 | |
| 2 Input 2 Bit Muxes := 1 | |
| 2 Input 1 Bit Muxes := 12 | |
| --------------------------------------------------------------------------------- | |
| Finished RTL Hierarchical Component Statistics | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Part Resource Summary | |
| --------------------------------------------------------------------------------- | |
| Part Resources: | |
| DSPs: 3600 (col length:200) | |
| BRAMs: 2940 (col length: RAMB18 200 RAMB36 100) | |
| --------------------------------------------------------------------------------- | |
| Finished Part Resource Summary | |
| --------------------------------------------------------------------------------- | |
| Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| Start Cross Boundary Optimization | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' into 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3033] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' into 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3033] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' into 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3033] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' into 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3033] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' into 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3033] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' into 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3033] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' into 'dct_2d_1_input_1d_stage_1_data_in_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3033] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[0][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[1][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' into 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3082] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[2][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:988] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1243] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[3][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[4][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_4_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_4_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1498] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_5_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_5_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1753] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[5][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[6][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_6_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_6_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2008] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_7_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_7_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2263] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' into 'dct_2d_1_dct_1d_1_output_sigs_reg[7][10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3096] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_8_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_8_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2518] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_9_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_9_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2773] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' into 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3082] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:988] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:988] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1243] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' into 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3082] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' into 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3082] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_4_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_4_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1498] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1243] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:988] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:988] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1243] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_4_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_4_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1498] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_5_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_5_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1753] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' into 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3082] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' into 'dct_2d_1_dct_1d_1_data_in_reg_reg[8:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:3082] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_6_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_6_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:2008] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_5_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_5_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1753] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_4_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_4_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1498] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_3_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:1243] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:988] | |
| INFO: [Synth 8-4471] merging register 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' into 'dct_2d_1_dct_1d_2_data_in_reg_reg[10:0]' [C:/Users/VLSILAB/Desktop/jpeg_measurements/project_1/project_1.srcs/sources_1/imports/jpeg_measurements/frontend_top_level_v2.vhd:988] | |
| INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_1_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_input_1d_stage_1_data_in_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_1_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_1_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_1_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_2_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_2_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_2_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_2_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_1_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_input_1d_stage_1_data_in_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_3_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_3_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_3_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_3_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_2_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_2_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_2_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_2_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_2_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_2_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_2_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_2_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_2_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_2_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_3_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_3_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_3_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_3_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_3_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_1_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_input_1d_stage_1_data_in_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_4_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_4_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_4_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_4_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_1_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_input_1d_stage_1_data_in_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_5_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_5_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_5_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_5_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_4_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_4_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_4_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_4_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_4_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_3_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_3_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_3_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_3_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_3_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_2_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_2_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_2_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_2_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_2_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_2_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_2_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_2_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_2_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_2_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_3_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_3_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_3_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_3_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_3_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_4_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_4_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_4_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_4_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_4_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_5_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_5_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_5_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_5_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_5_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_1_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_input_1d_stage_1_data_in_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_6_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_6_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_6_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_6_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_1_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_input_1d_stage_1_data_in_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_7_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_7_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_7_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_7_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_6_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_6_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_6_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_6_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_6_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_5_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_5_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_5_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_5_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_5_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_4_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_4_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_4_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_4_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_4_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_3_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_3_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_3_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_3_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_3_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_2_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_2_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_2_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_2_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_2_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_2_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_2_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_2_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_2_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_2_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_3_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_3_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_3_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_3_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_3_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_4_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_4_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_4_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_4_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_4_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_5_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_5_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_5_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_5_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_5_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_6_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_6_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_6_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_6_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_6_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_7_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_7_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_7_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_7_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_7_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_1_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_input_1d_stage_1_data_in_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_1_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_1_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_1_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_1_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_8_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_8_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_8_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_8_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_1_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_input_1d_stage_1_data_in_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_1_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_1_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_1_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_1_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_1_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_1_adder_reg_reg[7]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_9_adder_reg_reg[0], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_9_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_9_adder_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[0]. | |
| DSP Report: register dct_2d_1_dct_1d_9_mult_reg_reg[0] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_adder_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[0]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_mult_reg_reg[0]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[0]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_8_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_8_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_8_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_8_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_8_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_7_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_7_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_7_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_7_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_7_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_6_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_6_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_6_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_6_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_6_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_5_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_5_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_5_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_5_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_5_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_4_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_4_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_4_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_4_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_4_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_3_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_3_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_3_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_3_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_3_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_2_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[0] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_2_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_2_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_2_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_2_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_2_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_2_adder_reg_reg[7]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_3_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_3_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_3_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_3_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_3_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_3_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_3_adder_reg_reg[7]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_4_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_4_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_4_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_4_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_4_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_5_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_5_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_5_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_5_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_5_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_6_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_6_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_6_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_6_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_6_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_7_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_7_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_7_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_7_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_7_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_8_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_8_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_8_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_8_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_8_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_9_adder_reg_reg[1], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_9_coeffs_reg[1] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_9_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_9_adder_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[1]. | |
| DSP Report: register dct_2d_1_dct_1d_9_mult_reg_reg[1] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_adder_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[1]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_mult_reg_reg[1]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[1]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_9_adder_reg_reg[2], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_9_coeffs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_9_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_9_adder_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[2]. | |
| DSP Report: register dct_2d_1_dct_1d_9_mult_reg_reg[2] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_adder_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[2]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_mult_reg_reg[2]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[2]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_8_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_8_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_8_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_8_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_8_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_7_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_7_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_7_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_7_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_7_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_6_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_6_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_6_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_6_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_6_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_5_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_5_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_5_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_5_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_5_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_4_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[2] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_4_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_4_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_4_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_4_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_4_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_4_adder_reg_reg[7]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_5_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_5_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_5_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_5_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_5_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_5_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_5_adder_reg_reg[7]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_6_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_6_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_6_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_6_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_6_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_7_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_7_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_7_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_7_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_7_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_8_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_8_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_8_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_8_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_8_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_9_adder_reg_reg[3], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_9_coeffs_reg[3] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_9_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_9_adder_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[3]. | |
| DSP Report: register dct_2d_1_dct_1d_9_mult_reg_reg[3] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_adder_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[3]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_mult_reg_reg[3]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[3]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_9_adder_reg_reg[4], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_9_coeffs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_9_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_9_adder_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[4]. | |
| DSP Report: register dct_2d_1_dct_1d_9_mult_reg_reg[4] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_adder_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[4]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_mult_reg_reg[4]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[4]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_8_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_8_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_8_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_8_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_8_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_7_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_7_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_7_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_7_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_7_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_6_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[4] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_6_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_6_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_6_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_6_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_6_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_6_adder_reg_reg[7]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_7_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_7_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_7_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_7_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_7_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_7_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_7_adder_reg_reg[7]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_8_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_8_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_8_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_8_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_8_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_9_adder_reg_reg[5], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_9_coeffs_reg[5] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_9_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_9_adder_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[5]. | |
| DSP Report: register dct_2d_1_dct_1d_9_mult_reg_reg[5] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_adder_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[5]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_mult_reg_reg[5]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[5]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_9_adder_reg_reg[6], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_9_coeffs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_9_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_9_adder_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[6]. | |
| DSP Report: register dct_2d_1_dct_1d_9_mult_reg_reg[6] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_adder_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[6]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_mult_reg_reg[6]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[6]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_8_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[6] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_8_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_8_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_8_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_8_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_8_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_8_adder_reg_reg[7]. | |
| DSP Report: Generating DSP dct_2d_1_dct_1d_9_adder_reg_reg[7], operation Mode is: (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')'. | |
| DSP Report: register dct_2d_1_dct_1d_1_output_sigs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_9_data_in_reg_reg is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_9_coeffs_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_9_adder_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[7]. | |
| DSP Report: register dct_2d_1_dct_1d_9_mult_reg_reg[7] is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_adder_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[7]. | |
| DSP Report: operator dct_2d_1_dct_1d_9_mult_reg_reg[7]0 is absorbed into DSP dct_2d_1_dct_1d_9_adder_reg_reg[7]. | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port outputs_end_of_block_conversion | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_color_mode[1] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_color_mode[0] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[7] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[6] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[5] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[4] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[3] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[2] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[1] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_red[0] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[7] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[6] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[5] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[4] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[3] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[2] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[1] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_green[0] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[7] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[6] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[5] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[4] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[3] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[2] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[1] | |
| WARNING: [Synth 8-3331] design frontend_top_level_v2 has unconnected port inputs_blue[0] | |
| --------------------------------------------------------------------------------- | |
| Finished Cross Boundary Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| Finished Parallel Reinference : Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| Sort Area is null dct_2d_1_dct_1d_2_adder_reg_reg[1]_49 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_2_adder_reg_reg[2]_48 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_2_adder_reg_reg[3]_42 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_2_adder_reg_reg[4]_41 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_2_adder_reg_reg[5]_37 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_2_adder_reg_reg[6]_36 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_2_adder_reg_reg[7]_27 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_3_adder_reg_reg[1]_47 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_3_adder_reg_reg[2]_43 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_3_adder_reg_reg[3]_40 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_3_adder_reg_reg[4]_38 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_3_adder_reg_reg[5]_35 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_3_adder_reg_reg[6]_28 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_3_adder_reg_reg[7]_24 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_4_adder_reg_reg[1]_44 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_4_adder_reg_reg[2]_3f : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_4_adder_reg_reg[3]_39 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_4_adder_reg_reg[4]_34 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_4_adder_reg_reg[5]_29 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_4_adder_reg_reg[6]_22 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_4_adder_reg_reg[7]_17 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_5_adder_reg_reg[1]_3e : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_5_adder_reg_reg[2]_3a : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_5_adder_reg_reg[3]_33 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_5_adder_reg_reg[4]_2a : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_5_adder_reg_reg[5]_21 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_5_adder_reg_reg[6]_18 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_5_adder_reg_reg[7]_15 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_6_adder_reg_reg[1]_3b : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_6_adder_reg_reg[2]_32 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_6_adder_reg_reg[3]_2b : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_6_adder_reg_reg[4]_20 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_6_adder_reg_reg[5]_19 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_6_adder_reg_reg[6]_13 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_6_adder_reg_reg[7]_c : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_7_adder_reg_reg[1]_31 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_7_adder_reg_reg[2]_2c : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_7_adder_reg_reg[3]_1f : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_7_adder_reg_reg[4]_1a : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_7_adder_reg_reg[5]_12 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_7_adder_reg_reg[6]_d : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_7_adder_reg_reg[7]_a : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_8_adder_reg_reg[1]_2d : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_8_adder_reg_reg[2]_1e : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_8_adder_reg_reg[3]_1b : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_8_adder_reg_reg[4]_11 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_8_adder_reg_reg[5]_e : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_8_adder_reg_reg[6]_8 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_8_adder_reg_reg[7]_5 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_9_adder_reg_reg[1]_1d : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_9_adder_reg_reg[2]_1c : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_9_adder_reg_reg[3]_10 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_9_adder_reg_reg[4]_f : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_9_adder_reg_reg[5]_7 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_9_adder_reg_reg[6]_6 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_9_adder_reg_reg[7]_2 : 0 0 : 1371 1371 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_2_adder_reg_reg[0]_4b : 0 0 : 1356 1356 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_3_adder_reg_reg[0]_4a : 0 0 : 1356 1356 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_4_adder_reg_reg[0]_46 : 0 0 : 1356 1356 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_5_adder_reg_reg[0]_45 : 0 0 : 1356 1356 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_6_adder_reg_reg[0]_3d : 0 0 : 1356 1356 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_7_adder_reg_reg[0]_3c : 0 0 : 1356 1356 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_8_adder_reg_reg[0]_30 : 0 0 : 1356 1356 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_9_adder_reg_reg[0]_2e : 0 0 : 1356 1356 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_1_adder_reg_reg[1]_23 : 0 0 : 1085 1085 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_1_adder_reg_reg[2]_16 : 0 0 : 1085 1085 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_1_adder_reg_reg[3]_14 : 0 0 : 1085 1085 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_1_adder_reg_reg[4]_b : 0 0 : 1085 1085 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_1_adder_reg_reg[5]_9 : 0 0 : 1085 1085 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_1_adder_reg_reg[6]_4 : 0 0 : 1085 1085 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_1_adder_reg_reg[7]_0 : 0 0 : 1085 1085 : Used 1 time 0 | |
| Sort Area is null dct_2d_1_dct_1d_1_adder_reg_reg[0]_25 : 0 0 : 1070 1070 : Used 1 time 0 | |
| --------------------------------------------------------------------------------- | |
| Start RAM, DSP and Shift Register Reporting | |
| --------------------------------------------------------------------------------- | |
| DSP: | |
| +----------------------+-------------------------------------------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | |
| |Module Name | DSP Mapping | Neg Edge Clk | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | | |
| +----------------------+-------------------------------------------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 9 | 25 | 25 | 25 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 9 | 25 | 25 | 25 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 9 | 25 | 25 | 25 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 9 | 25 | 25 | 25 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 9 | 25 | 25 | 25 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 9 | 25 | 25 | 25 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 9 | 25 | 25 | 25 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 9 | 25 | 25 | 25 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 0 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| |frontend_top_level_v2 | (((EDGE:1=>(C:0x0)) or (EDGE:0=>P))+(A2*B'')')' | No | 15 | 11 | 27 | 25 | 27 | 1 | 2 | 0 | 1 | 1 | 1 | 1 | | |
| +----------------------+-------------------------------------------------+--------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | |
| Note: The table shows DSPs generated at current stage. Some DSP generation could be reversed due to later optimizations. Multiple instantiated DSPs are reported only once. | |
| --------------------------------------------------------------------------------- | |
| Finished RAM, DSP and Shift Register Reporting | |
| --------------------------------------------------------------------------------- | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[1] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[1] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[2] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[2] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[3] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[3] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[4] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[4] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[5] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[5] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[6] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[6] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[7] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[7] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[8] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[8] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[9] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[9] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[10] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[10] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[11] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[11] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[12] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[12] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[13] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[13] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[14] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[14] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[15] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[15] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[16] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[16] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[17] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[17] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[18] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[18] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[19] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[19] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[20] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[20] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[21] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[21] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][14] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\dct_2d_1_data_in_signed_reg[8] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][14] ) | |
| INFO: [Synth 8-3333] propagating constant 0 across sequential element (\dct_2d_input_data_in_reg[7] ) | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_input_data_in_reg[7] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_input_data_in_reg[6] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_input_data_in_reg[5] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_input_data_in_reg[4] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_input_data_in_reg[3] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_input_data_in_reg[2] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_input_data_in_reg[1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_input_data_in_reg[0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][14] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][13] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][11] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][10] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][9] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][8] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][7] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][6] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][5] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][4] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][3] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][2] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_2_coeffs_reg[0][0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][14] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][13] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][11] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][10] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][9] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][8] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][7] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][6] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][5] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][4] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][3] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][2] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_dct_1d_1_coeffs_reg[0][0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[8] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[7] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[6] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[5] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[4] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[3] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[2] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\dct_2d_1_data_in_signed_reg[0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\input_counter_reg[5] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\input_counter_reg[4] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\input_counter_reg[3] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\input_counter_reg[2] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\input_counter_reg[1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\input_counter_reg[0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\color_mode_reg[1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\color_mode_reg[0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\inputs_reg_color_mode_reg[1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\inputs_reg_color_mode_reg[0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_color_mode_reg_reg[1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_color_mode_reg_reg[0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[23] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[22] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[21] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[20] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[19] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[18] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[17] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[16] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[15] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[14] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[13] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[12] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[11] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[10] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[9] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[8] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[7] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[6] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[5] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[4] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[3] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[2] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[1] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_second_adder_sum_reg[0] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[23] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[22] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[21] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[20] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[19] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[18] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[17] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[16] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[15] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[14] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[13] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[12] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[11] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[10] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[9] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[8] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[7] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[6] ) is unused and will be removed from module frontend_top_level_v2. | |
| WARNING: [Synth 8-3332] Sequential element (\rgb2ycbcr_v2_1_first_adder_sum_reg[5] ) is unused and will be removed from module frontend_top_level_v2. | |
| INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| --------------------------------------------------------------------------------- | |
| Start Area Optimization | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| Finished Parallel Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| Start Timing Optimization | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Applying XDC Timing Constraints | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:51 ; elapsed = 00:00:54 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Timing Optimization : Time (s): cpu = 00:00:52 ; elapsed = 00:00:56 . Memory (MB): peak = 809.703 ; gain = 611.129 | |
| --------------------------------------------------------------------------------- | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start Technology Mapping | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Technology Mapping : Time (s): cpu = 00:00:54 ; elapsed = 00:00:58 . Memory (MB): peak = 825.219 ; gain = 626.645 | |
| --------------------------------------------------------------------------------- | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start IO Insertion | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Flattening Before IO Insertion | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Flattening Before IO Insertion | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Final Netlist Cleanup | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Final Netlist Cleanup | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished IO Insertion : Time (s): cpu = 00:00:55 ; elapsed = 00:00:58 . Memory (MB): peak = 825.219 ; gain = 626.645 | |
| --------------------------------------------------------------------------------- | |
| Report Check Netlist: | |
| +------+------------------+-------+---------+-------+------------------+ | |
| | |Item |Errors |Warnings |Status |Description | | |
| +------+------------------+-------+---------+-------+------------------+ | |
| |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | | |
| +------+------------------+-------+---------+-------+------------------+ | |
| --------------------------------------------------------------------------------- | |
| Start Renaming Generated Instances | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Renaming Generated Instances : Time (s): cpu = 00:00:55 ; elapsed = 00:00:58 . Memory (MB): peak = 825.219 ; gain = 626.645 | |
| --------------------------------------------------------------------------------- | |
| Report RTL Partitions: | |
| +-+--------------+------------+----------+ | |
| | |RTL Partition |Replication |Instances | | |
| +-+--------------+------------+----------+ | |
| +-+--------------+------------+----------+ | |
| --------------------------------------------------------------------------------- | |
| Start Rebuilding User Hierarchy | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:56 ; elapsed = 00:00:59 . Memory (MB): peak = 825.219 ; gain = 626.645 | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start RAM, DSP and Shift Register Reporting | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Finished RAM, DSP and Shift Register Reporting | |
| --------------------------------------------------------------------------------- | |
| --------------------------------------------------------------------------------- | |
| Start Writing Synthesis Report | |
| --------------------------------------------------------------------------------- | |
| Report BlackBoxes: | |
| +-+--------------+----------+ | |
| | |BlackBox name |Instances | | |
| +-+--------------+----------+ | |
| +-+--------------+----------+ | |
| Report Cell Usage: | |
| +------+----------+------+ | |
| | |Cell |Count | | |
| +------+----------+------+ | |
| |1 |BUFG | 1| | |
| |2 |CARRY4 | 216| | |
| |3 |DSP48E1 | 9| | |
| |4 |DSP48E1_1 | 63| | |
| |5 |LUT1 | 766| | |
| |6 |LUT2 | 138| | |
| |7 |LUT3 | 256| | |
| |8 |LUT4 | 12| | |
| |9 |LUT5 | 11| | |
| |10 |LUT6 | 197| | |
| |11 |MUXF7 | 88| | |
| |12 |MUXF8 | 44| | |
| |13 |FDRE | 1512| | |
| |14 |LD | 2| | |
| |15 |IBUF | 3| | |
| |16 |OBUF | 12| | |
| +------+----------+------+ | |
| Report Instance Areas: | |
| +------+---------+-------+------+ | |
| | |Instance |Module |Cells | | |
| +------+---------+-------+------+ | |
| |1 |top | | 3330| | |
| +------+---------+-------+------+ | |
| --------------------------------------------------------------------------------- | |
| Finished Writing Synthesis Report : Time (s): cpu = 00:00:56 ; elapsed = 00:00:59 . Memory (MB): peak = 825.219 ; gain = 626.645 | |
| --------------------------------------------------------------------------------- | |
| Synthesis finished with 0 errors, 0 critical warnings and 173 warnings. | |
| Synthesis Optimization Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:41 . Memory (MB): peak = 825.219 ; gain = 95.996 | |
| Synthesis Optimization Complete : Time (s): cpu = 00:00:56 ; elapsed = 00:00:59 . Memory (MB): peak = 825.219 ; gain = 626.645 | |
| INFO: [Project 1-571] Translating synthesized netlist | |
| INFO: [Netlist 29-17] Analyzing 293 Unisim elements for replacement | |
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |
| WARNING: [Netlist 29-101] Netlist 'frontend_top_level_v2' is not ideal for floorplanning, since the cellview 'frontend_top_level_v2' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. | |
| INFO: [Project 1-570] Preparing netlist for logic optimization | |
| INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. | |
| INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. | |
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
| INFO: [Project 1-111] Unisim Transformation Summary: | |
| A total of 2 instances were transformed. | |
| LD => LDCE: 2 instances | |
| INFO: [Common 17-83] Releasing license: Synthesis | |
| 200 Infos, 270 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| synth_design completed successfully | |
| synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:00:59 . Memory (MB): peak = 825.219 ; gain = 626.645 | |
| INFO: [Common 17-600] The following parameters have non-default value. | |
| general.maxThreads | |
| # write_checkpoint -noxdef frontend_top_level_v2.dcp | |
| # catch { report_utilization -file frontend_top_level_v2_utilization_synth.rpt -pb frontend_top_level_v2_utilization_synth.pb } | |
| report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.195 . Memory (MB): peak = 825.219 ; gain = 0.000 | |
| INFO: [Common 17-206] Exiting Vivado at Sat Jul 23 10:58:51 2016... |
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