utilization_report

Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
| Date         : Sat Jul 23 10:58:51 2016
| Host         : VLSILAB-STRIKE running 64-bit Service Pack 1  (build 7601)
| Command      : report_utilization -file frontend_top_level_v2_utilization_synth.rpt -pb frontend_top_level_v2_utilization_synth.pb
| Design       : frontend_top_level_v2
| Device       : xc7vx690t
| Design State : Synthesized
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Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists

1. Slice Logic
--------------

+-------------------------+------+-------+-----------+-------+
|        Site Type        | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs*             | 1380 |     0 |    433200 |  0.31 |
|   LUT as Logic          | 1380 |     0 |    433200 |  0.31 |
|   LUT as Memory         |    0 |     0 |    174200 |  0.00 |
| Slice Registers         | 1514 |     0 |    866400 |  0.17 |
|   Register as Flip Flop | 1512 |     0 |    866400 |  0.17 |
|   Register as Latch     |    2 |     0 |    866400 | <0.01 |
| F7 Muxes                |   88 |     0 |    216600 |  0.04 |
| F8 Muxes                |   44 |     0 |    108300 |  0.04 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 0     |          Yes |           - |          Set |
| 2     |          Yes |           - |        Reset |
| 0     |          Yes |         Set |            - |
| 1512  |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. Memory
---------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile |    0 |     0 |      1470 |  0.00 |
|   RAMB36/FIFO* |    0 |     0 |      1470 |  0.00 |
|   RAMB18       |    0 |     0 |      2940 |  0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


3. DSP
------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs           |   72 |     0 |      3600 |  2.00 |
|   DSP48E1 only |   72 |       |           |       |
+----------------+------+-------+-----------+-------+


4. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+-------+
|          Site Type          | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB                  |   15 |     0 |       850 |  1.76 |
| Bonded IPADs                |    0 |     0 |       110 |  0.00 |
| Bonded OPADs                |    0 |     0 |        72 |  0.00 |
| PHY_CONTROL                 |    0 |     0 |        20 |  0.00 |
| PHASER_REF                  |    0 |     0 |        20 |  0.00 |
| OUT_FIFO                    |    0 |     0 |        80 |  0.00 |
| IN_FIFO                     |    0 |     0 |        80 |  0.00 |
| IDELAYCTRL                  |    0 |     0 |        20 |  0.00 |
| IBUFGDS                     |    0 |     0 |       816 |  0.00 |
| GTHE2_CHANNEL               |    0 |     0 |        36 |  0.00 |
| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        80 |  0.00 |
| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        80 |  0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |      1000 |  0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY |    0 |     0 |      1000 |  0.00 |
| IBUFDS_GTE2                 |    0 |     0 |        40 |  0.00 |
| ILOGIC                      |    0 |     0 |       850 |  0.00 |
| OLOGIC                      |    0 |     0 |       850 |  0.00 |
+-----------------------------+------+-------+-----------+-------+


5. Clocking
-----------

+------------+------+-------+-----------+-------+
|  Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL   |    1 |     0 |        32 |  3.12 |
| BUFIO      |    0 |     0 |        80 |  0.00 |
| MMCME2_ADV |    0 |     0 |        20 |  0.00 |
| PLLE2_ADV  |    0 |     0 |        20 |  0.00 |
| BUFMRCE    |    0 |     0 |        40 |  0.00 |
| BUFHCE     |    0 |     0 |       240 |  0.00 |
| BUFR       |    0 |     0 |        80 |  0.00 |
+------------+------+-------+-----------+-------+


6. Specific Feature
-------------------

+-------------+------+-------+-----------+-------+
|  Site Type  | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2     |    0 |     0 |         4 |  0.00 |
| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
| DNA_PORT    |    0 |     0 |         1 |  0.00 |
| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
| ICAPE2      |    0 |     0 |         2 |  0.00 |
| PCIE_3_0    |    0 |     0 |         3 |  0.00 |
| STARTUPE2   |    0 |     0 |         1 |  0.00 |
| XADC        |    0 |     0 |         1 |  0.00 |
+-------------+------+-------+-----------+-------+


7. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE     | 1512 |        Flop & Latch |
| LUT1     |  766 |                 LUT |
| LUT3     |  256 |                 LUT |
| CARRY4   |  216 |          CarryLogic |
| LUT6     |  197 |                 LUT |
| LUT2     |  138 |                 LUT |
| MUXF7    |   88 |               MuxFx |
| DSP48E1  |   72 |    Block Arithmetic |
| MUXF8    |   44 |               MuxFx |
| OBUF     |   12 |                  IO |
| LUT4     |   12 |                 LUT |
| LUT5     |   11 |                 LUT |
| IBUF     |    3 |                  IO |
| LDCE     |    2 |        Flop & Latch |
| BUFG     |    1 |               Clock |
+----------+------+---------------------+


8. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


9. Instantiated Netlists
------------------------

+----------+------+
| Ref Name | Used |
+----------+------+