Migen Cat With inouts Generates Invalid Verilog

cat.py

from migen import *
from migen.fhdl import verilog

class CatTest(Module):
    def __init__(self):
        self.a = Signal(1)
        self.b = Signal(1)
        self.c = Cat([self.a, self.b])
        self.d = Signal(2)
        
        self.iobufs = [TSTriple() for i in range(2)]
        self.iopad_a = Signal(1)
        self.iopad_b = Signal(1)
        self.iopads = Cat([self.iopad_a, self.iopad_b])
        
        self.comb += [self.c[i].eq(self.d[i]) for i in range(flen(self.d))]
        self.specials += [self.iobufs[i].get_tristate(self.iopads[i])
            for i in range(flen(self.iopads))]

m = CatTest()
print(verilog.convert(m, ios = {m.a, m.b, m.iopad_a, m.iopad_b}))

cat.v

/* Machine-generated using Migen */
module top(
	output reg a,
	output reg b,
	inout iopad_a,
	inout iopad_b
);

reg [1:0] d = 1'd0;
reg tstriple0_o = 1'd0;
reg tstriple0_oe = 1'd0;
wire tstriple0_i;
reg tstriple1_o = 1'd0;
reg tstriple1_oe = 1'd0;
wire tstriple1_i;
wire [1:0] slice_proxy0;
wire [1:0] slice_proxy1;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign slice_proxy0[0] = d[0];
assign slice_proxy1[1] = d[1];

// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
	a <= 1'd0;
	b <= 1'd0;
	{b, a} <= slice_proxy0;
	{b, a} <= slice_proxy1;
// synthesis translate_off
	dummy_d <= dummy_s;
// synthesis translate_on
end

assign {iopad_b, iopad_a}[0] = tstriple0_oe ? tstriple0_o : 1'bz;
assign tstriple0_i = {iopad_b, iopad_a}[0];

assign {iopad_b, iopad_a}[1] = tstriple1_oe ? tstriple1_o : 1'bz;
assign tstriple1_i = {iopad_b, iopad_a}[1];

endmodule