Mercury XCVR

mercxcvr.py

class MercXCVRs(Module):
    def __init__(self, pads):
        self.pin_in = Signal(30)  # Create the input bus from the FPGA pins
        self.pin_out = Signal(30) # The output bus to the FPGA pins
        self.pin_oe = Signal(30)  # Output enable for FPGA pins         
        self.iobufs = [TSTriple() for i in range(30)]
        # self.pins = pads.raw_bits()
        self.mem_cen = Signal(1)
        self.bussw_oen = Signal(1)
        
        ###
        self.comb += [pads.ce_n.eq(self.mem_cen)]
        self.comb += [pads.bussw_oe_n.eq(self.bussw_oen)]

        for i in range(30):
            self.comb += [self.pin_in[i].eq(self.iobufs[i].i)]
            self.comb += [self.iobufs[i].o.eq(self.pin_out[i])]
            self.comb += [self.iobufs[i].oe.eq(self.pin_oe[i])]
            # self.specials += [self.iobufs[i].get_tristate(self.pins[i])]
            # Fix when https://github.com/m-labs/migen/issues/20 is solved

        start = 0
        for subsig, _ in pads.iter_flat():
           siglen = flen(subsig)
           for i in range(siglen):
               self.specials += [self.iobufs[start + i].get_tristate(subsig[i])]
           start += siglen
           if(start >= 30): # iter_flat() is generator... only need 30 out of 32 signals.
               break