IceStick PLL Example

icestick_pll.v

/* Machine-generated using Migen */
module top(
	output gpio,
	output user_led,
	input clk12
);

wire __main___pll_outg;
wire __main___lock;
wire sys_clk;
reg sys_rst = 1'd0;
wire gen_clk;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign user_led = __main___lock;
assign sys_clk = clk12;
assign gpio = gen_clk;

SB_PLL40_CORE #(
	.DIVF(7'd87),
	.DIVQ(2'd2),
	.DIVR(1'd0),
	.FILTER_RANGE(3'd1)
) SB_PLL40_CORE (
	.REFERENCECLK(sys_clk),
	.RESETB((~sys_rst)),
	.LOCK(__main___lock),
	.PLLOUTGLOBAL(__main___pll_outg)
);

SB_GB SB_GB(
	.USER_SIGNAL_TO_GLOBAL_BUFFER(__main___pll_outg),
	.GLOBAL_BUFFER_OUTPUT(gen_clk)
);

endmodule