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cr1901/shift-reg-inst.v

Last active August 13, 2016 15:59
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Shift Reg Inference
Raw
shift-reg-inst.v
module top(
clk,
sin,
bit0,
bit1,
bit2,
bit3,
bit4,
bit5,
bit6,
bit7,
bit8,
bit9,
bita,
bitb,
bitc,
bitd,
bite,
bitf
);
input wire clk;
input wire sin;
output wire bit0;
output wire bit1;
output wire bit2;
output wire bit3;
output wire bit4;
output wire bit5;
output wire bit6;
output wire bit7;
output wire bit8;
output wire bit9;
output wire bita;
output wire bitb;
output wire bitc;
output wire bitd;
output wire bite;
output wire bitf;
`ifdef NO_INFER_GP_SHREG_AT_ALL
reg[0:11] shift_hi = 12'b1; // Force non-instantiation.
wire[0:1] shift_mid_taps;
`else
reg[0:11] shift_hi;
reg[0:1] shift_mid_taps;
`endif
wire[0:1] shift_lo_taps;
assign {bit0, bit1} = shift_lo_taps;
assign {bit2, bit3} = shift_mid_taps;
assign {bit4,
bit5,
bit6,
bit7,
bit8,
bit9,
bita,
bitb,
bitc,
bitd,
bite,
bitf
} = shift_hi;
GP_SHREG #(
.OUTA_TAP(1),
.OUTA_INVERT(0),
.OUTB_TAP(2)
) shift_lo (
.nRST(1'b1),
.CLK(clk),
.IN(sin),
.OUTA(shift_lo_taps[0]),
.OUTB(shift_lo_taps[1])
);
`ifdef NO_INFER_GP_SHREG_AT_ALL
GP_SHREG #(
.OUTA_TAP(0),
.OUTA_INVERT(0),
.OUTB_TAP(1)
) shift_mid (
.nRST(1'b1),
.CLK(clk),
.IN(shift_lo_taps[1]),
.OUTA(shift_mid_taps[0]),
.OUTB(shift_mid_taps[1])
);
`endif
always @(posedge clk) begin
shift_hi = {shift_mid_taps[1], shift_hi[0:10]};
`ifndef NO_INFER_GP_SHREG_AT_ALL
shift_mid_taps = {shift_lo_taps[0], shift_mid_taps[0]};
`endif
end
endmodule
Raw
shift-reg.json
{
"creator": "Yosys 0.6+193 (git sha1 0515809, gcc 4.8.4-2ubuntu1~14.04.3 -fPIC -Os)",
"modules": {
"GP_2LUT": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:3"
},
"ports": {
"IN0": {
"direction": "input",
"bits": [ 2 ]
},
"IN1": {
"direction": "input",
"bits": [ 3 ]
},
"OUT": {
"direction": "output",
"bits": [ 4 ]
}
},
"cells": {
},
"netnames": {
"IN0": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:3"
}
},
"IN1": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:3"
}
},
"OUT": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:3"
}
}
}
},
"GP_3LUT": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:8"
},
"ports": {
"IN0": {
"direction": "input",
"bits": [ 2 ]
},
"IN1": {
"direction": "input",
"bits": [ 3 ]
},
"IN2": {
"direction": "input",
"bits": [ 4 ]
},
"OUT": {
"direction": "output",
"bits": [ 5 ]
}
},
"cells": {
},
"netnames": {
"IN0": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:8"
}
},
"IN1": {
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"attributes": {
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}
},
"IN2": {
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"attributes": {
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}
},
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}
}
}
},
"GP_4LUT": {
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},
"ports": {
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"direction": "input",
"bits": [ 2 ]
},
"IN1": {
"direction": "input",
"bits": [ 3 ]
},
"IN2": {
"direction": "input",
"bits": [ 4 ]
},
"IN3": {
"direction": "input",
"bits": [ 5 ]
},
"OUT": {
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"bits": [ 6 ]
}
},
"cells": {
},
"netnames": {
"IN0": {
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"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:13"
}
},
"IN1": {
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"bits": [ 3 ],
"attributes": {
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}
},
"IN2": {
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"attributes": {
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}
},
"IN3": {
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"attributes": {
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}
},
"OUT": {
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"attributes": {
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}
}
}
},
"GP_ABUF": {
"attributes": {
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"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:18"
},
"ports": {
"IN": {
"direction": "input",
"bits": [ 2 ]
},
"OUT": {
"direction": "output",
"bits": [ 3 ]
}
},
"cells": {
},
"netnames": {
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"bits": [ 2 ],
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}
},
"OUT": {
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"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:18"
}
}
}
},
"GP_ACMP": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:26"
},
"ports": {
"PWREN": {
"direction": "input",
"bits": [ 2 ]
},
"VIN": {
"direction": "input",
"bits": [ 3 ]
},
"VREF": {
"direction": "input",
"bits": [ 4 ]
},
"OUT": {
"direction": "output",
"bits": [ 5 ]
}
},
"cells": {
},
"netnames": {
"OUT": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:26"
}
},
"PWREN": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:26"
}
},
"VIN": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:26"
}
},
"VREF": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:26"
}
}
}
},
"GP_BANDGAP": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:39"
},
"ports": {
"OK": {
"direction": "output",
"bits": [ 2 ]
}
},
"cells": {
},
"netnames": {
"OK": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:39"
}
}
}
},
"GP_COUNT14": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:86"
},
"ports": {
"CLK": {
"direction": "input",
"bits": [ 2 ]
},
"RST": {
"direction": "input",
"bits": [ 3 ]
},
"OUT": {
"direction": "output",
"bits": [ 4 ]
}
},
"cells": {
},
"netnames": {
"CLK": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:86"
}
},
"OUT": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:86"
}
},
"RST": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:86"
}
}
}
},
"GP_COUNT14_ADV": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:110"
},
"ports": {
"CLK": {
"direction": "input",
"bits": [ 2 ]
},
"RST": {
"direction": "input",
"bits": [ 3 ]
},
"OUT": {
"direction": "output",
"bits": [ 4 ]
},
"UP": {
"direction": "input",
"bits": [ 5 ]
},
"KEEP": {
"direction": "input",
"bits": [ 6 ]
}
},
"cells": {
},
"netnames": {
"CLK": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:110"
}
},
"KEEP": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:111"
}
},
"OUT": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:110"
}
},
"RST": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:110"
}
},
"UP": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:111"
}
}
}
},
"GP_COUNT8": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:48"
},
"ports": {
"CLK": {
"direction": "input",
"bits": [ 2 ]
},
"RST": {
"direction": "input",
"bits": [ 3 ]
},
"OUT": {
"direction": "output",
"bits": [ 4 ]
}
},
"cells": {
},
"netnames": {
"CLK": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:48"
}
},
"OUT": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:48"
}
},
"RST": {
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"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:48"
}
}
}
},
"GP_COUNT8_ADV": {
"attributes": {
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"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:97"
},
"ports": {
"CLK": {
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"bits": [ 2 ]
},
"RST": {
"direction": "input",
"bits": [ 3 ]
},
"OUT": {
"direction": "output",
"bits": [ 4 ]
},
"UP": {
"direction": "input",
"bits": [ 5 ]
},
"KEEP": {
"direction": "input",
"bits": [ 6 ]
}
},
"cells": {
},
"netnames": {
"CLK": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:97"
}
},
"KEEP": {
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"bits": [ 6 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:98"
}
},
"OUT": {
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"attributes": {
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}
},
"RST": {
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"bits": [ 3 ],
"attributes": {
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}
},
"UP": {
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"bits": [ 5 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:98"
}
}
}
},
"GP_DAC": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:123"
},
"ports": {
"DIN": {
"direction": "input",
"bits": [ 2, 3, 4, 5, 6, 7, 8, 9 ]
},
"VREF": {
"direction": "input",
"bits": [ 10 ]
},
"VOUT": {
"direction": "output",
"bits": [ 11 ]
}
},
"cells": {
},
"netnames": {
"DIN": {
"hide_name": 0,
"bits": [ 2, 3, 4, 5, 6, 7, 8, 9 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:123"
}
},
"VOUT": {
"hide_name": 0,
"bits": [ 11 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:123"
}
},
"VREF": {
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"bits": [ 10 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:123"
}
}
}
},
"GP_DELAY": {
"attributes": {
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"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:131"
},
"ports": {
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},
"OUT": {
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}
},
"cells": {
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}
},
"OUT": {
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"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:131"
}
}
}
},
"GP_DFF": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:160"
},
"ports": {
"D": {
"direction": "input",
"bits": [ 2 ]
},
"CLK": {
"direction": "input",
"bits": [ 3 ]
},
"Q": {
"direction": "output",
"bits": [ 4 ]
}
},
"cells": {
},
"netnames": {
"CLK": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:160"
}
},
"D": {
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"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:160"
}
},
"Q": {
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"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:160"
}
}
}
},
"GP_DFFR": {
"attributes": {
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},
"ports": {
"D": {
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"bits": [ 2 ]
},
"CLK": {
"direction": "input",
"bits": [ 3 ]
},
"nRST": {
"direction": "input",
"bits": [ 4 ]
},
"Q": {
"direction": "output",
"bits": [ 5 ]
}
},
"cells": {
},
"netnames": {
"CLK": {
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"bits": [ 3 ],
"attributes": {
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}
},
"D": {
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}
},
"Q": {
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"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:168"
}
},
"nRST": {
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"bits": [ 4 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:168"
}
}
}
},
"GP_DFFS": {
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},
"ports": {
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"bits": [ 2 ]
},
"CLK": {
"direction": "input",
"bits": [ 3 ]
},
"nSET": {
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"bits": [ 4 ]
},
"Q": {
"direction": "output",
"bits": [ 5 ]
}
},
"cells": {
},
"netnames": {
"CLK": {
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"bits": [ 3 ],
"attributes": {
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}
},
"D": {
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}
},
"Q": {
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"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:179"
}
},
"nSET": {
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"bits": [ 4 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:179"
}
}
}
},
"GP_DFFSR": {
"attributes": {
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"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:190"
},
"ports": {
"D": {
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"bits": [ 2 ]
},
"CLK": {
"direction": "input",
"bits": [ 3 ]
},
"nSR": {
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"bits": [ 4 ]
},
"Q": {
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"bits": [ 5 ]
}
},
"cells": {
},
"netnames": {
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"attributes": {
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}
},
"D": {
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}
},
"Q": {
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"bits": [ 5 ],
"attributes": {
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}
},
"nSR": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:190"
}
}
}
},
"GP_IBUF": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:202"
},
"ports": {
"IN": {
"direction": "input",
"bits": [ 2 ]
},
"OUT": {
"direction": "output",
"bits": [ 3 ]
}
},
"cells": {
},
"netnames": {
"IN": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:202"
}
},
"OUT": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:202"
}
}
}
},
"GP_INV": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:211"
},
"ports": {
"IN": {
"direction": "input",
"bits": [ 2 ]
},
"OUT": {
"direction": "output",
"bits": [ 3 ]
}
},
"cells": {
},
"netnames": {
"IN": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:211"
}
},
"OUT": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:211"
}
}
}
},
"GP_IOBUF": {
"attributes": {
"blackbox": 1,
"src": "/usr/local/bin/../share/yosys/greenpak4/cells_sim.v:206"
},
"ports": {
"IN": {
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"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 29 ],
"Q": [ 30 ]
}
},
"$auto$simplemap.cc:403:simplemap_dff$55": {
"hide_name": 1,
"type": "GP_DFF",
"parameters": {
"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 28 ],
"Q": [ 29 ]
}
},
"$auto$simplemap.cc:403:simplemap_dff$56": {
"hide_name": 1,
"type": "GP_DFF",
"parameters": {
"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 27 ],
"Q": [ 28 ]
}
},
"$auto$simplemap.cc:403:simplemap_dff$57": {
"hide_name": 1,
"type": "GP_DFF",
"parameters": {
"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 26 ],
"Q": [ 27 ]
}
},
"$auto$simplemap.cc:403:simplemap_dff$58": {
"hide_name": 1,
"type": "GP_DFF",
"parameters": {
"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 25 ],
"Q": [ 26 ]
}
},
"$auto$simplemap.cc:403:simplemap_dff$59": {
"hide_name": 1,
"type": "GP_DFF",
"parameters": {
"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 24 ],
"Q": [ 25 ]
}
},
"$auto$simplemap.cc:403:simplemap_dff$60": {
"hide_name": 1,
"type": "GP_DFF",
"parameters": {
"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 23 ],
"Q": [ 24 ]
}
},
"$auto$simplemap.cc:403:simplemap_dff$61": {
"hide_name": 1,
"type": "GP_DFF",
"parameters": {
"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 22 ],
"Q": [ 23 ]
}
},
"$auto$simplemap.cc:403:simplemap_dff$62": {
"hide_name": 1,
"type": "GP_DFF",
"parameters": {
"INIT": 0
},
"attributes": {
"src": "shift-reg/shift-reg.v:41"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 20 ],
"D": [ 21 ],
"Q": [ 22 ]
}
}
},
"netnames": {
"$auto$iopadmap.cc:313:execute$100": {
"hide_name": 1,
"bits": [ 20 ],
"attributes": {
}
},
"$auto$iopadmap.cc:313:execute$102": {
"hide_name": 1,
"bits": [ 21 ],
"attributes": {
}
},
"bit0": {
"hide_name": 0,
"bits": [ 4 ],
"attributes": {
}
},
"bit1": {
"hide_name": 0,
"bits": [ 5 ],
"attributes": {
}
},
"bit2": {
"hide_name": 0,
"bits": [ 6 ],
"attributes": {
}
},
"bit3": {
"hide_name": 0,
"bits": [ 7 ],
"attributes": {
}
},
"bit4": {
"hide_name": 0,
"bits": [ 8 ],
"attributes": {
}
},
"bit5": {
"hide_name": 0,
"bits": [ 9 ],
"attributes": {
}
},
"bit6": {
"hide_name": 0,
"bits": [ 10 ],
"attributes": {
}
},
"bit7": {
"hide_name": 0,
"bits": [ 11 ],
"attributes": {
}
},
"bit8": {
"hide_name": 0,
"bits": [ 12 ],
"attributes": {
}
},
"bit9": {
"hide_name": 0,
"bits": [ 13 ],
"attributes": {
}
},
"bita": {
"hide_name": 0,
"bits": [ 14 ],
"attributes": {
}
},
"bitb": {
"hide_name": 0,
"bits": [ 15 ],
"attributes": {
}
},
"bitc": {
"hide_name": 0,
"bits": [ 16 ],
"attributes": {
}
},
"bitd": {
"hide_name": 0,
"bits": [ 17 ],
"attributes": {
}
},
"bite": {
"hide_name": 0,
"bits": [ 18 ],
"attributes": {
}
},
"bitf": {
"hide_name": 0,
"bits": [ 19 ],
"attributes": {
}
},
"clk": {
"hide_name": 0,
"bits": [ 2 ],
"attributes": {
}
},
"shift_reg": {
"hide_name": 0,
"bits": [ 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22 ],
"attributes": {
}
},
"sin": {
"hide_name": 0,
"bits": [ 3 ],
"attributes": {
}
}
}
}
}
}
Raw
shift-reg.par
Device configuration:
Target device: SLG46620V
VCC range: not yet implemented
Unused pins: float
Loading Yosys JSON file "shift-reg/shift-reg.json".
Netlist creator: Yosys 0.6+193 (git sha1 0515809, gcc 4.8.4-2ubuntu1~14.04.3 -fPIC -Os)
Loading modules...
GP_2LUT
GP_3LUT
GP_4LUT
GP_ABUF
GP_ACMP
GP_BANDGAP
GP_COUNT14
GP_COUNT14_ADV
GP_COUNT8
GP_COUNT8_ADV
GP_DAC
GP_DELAY
GP_DFF
GP_DFFR
GP_DFFS
GP_DFFSR
GP_IBUF
GP_INV
GP_IOBUF
GP_LFOSC
GP_OBUF
GP_OBUFT
GP_PGA
GP_POR
GP_RCOSC
GP_RINGOSC
GP_SHREG
GP_SYSRESET
GP_VDD
GP_VREF
GP_VSS
top
Indexing...
Synthesizing top-level module "top".
Creating netlist graphs...
Replicating nodes to control hard IP dependencies...
XBPAR initializing...
Initial design feasibility check...
ERROR: Design is too big for the device (netlist has 14 nodes of type GP_DFF, device only has 12)
Placement report:
+----------------------------------------------------+-----------------+
| Node | Site |
+----------------------------------------------------+-----------------+
PAR failed
Raw
shift-reg.v
module top(
clk,
sin,
bit0,
bit1,
bit2,
bit3,
bit4,
bit5,
bit6,
bit7,
bit8,
bit9,
bita,
bitb,
bitc,
bitd,
bite,
bitf
);
input wire clk;
input wire sin;
output wire bit0;
output wire bit1;
output wire bit2;
output wire bit3;
output wire bit4;
output wire bit5;
output wire bit6;
output wire bit7;
output wire bit8;
output wire bit9;
output wire bita;
output wire bitb;
output wire bitc;
output wire bitd;
output wire bite;
output wire bitf;
reg[0:15] shift_reg;
assign {bit0,
bit1,
bit2,
bit3,
bit4,
bit5,
bit6,
bit7,
bit8,
bit9,
bita,
bitb,
bitc,
bitd,
bite,
bitf
} = shift_reg;
always @(posedge clk) begin
shift_reg = {sin, shift_reg[0:14]};
end
endmodule
Raw
shift-reg.yrp
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2016 Clifford Wolf <[email protected]> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.6+193 (git sha1 0515809, gcc 4.8.4-2ubuntu1~14.04.3 -fPIC -Os)
-- Parsing `shift-reg/shift-reg.v' using frontend `verilog' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `shift-reg/shift-reg.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.
-- Running command `synth_greenpak4 -top top -part SLG46620V;' --
2. Executing SYNTH_GREENPAK4 pass.
2.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/greenpak4/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\GP_2LUT'.
Generating RTLIL representation for module `\GP_3LUT'.
Generating RTLIL representation for module `\GP_4LUT'.
Generating RTLIL representation for module `\GP_ABUF'.
Generating RTLIL representation for module `\GP_ACMP'.
Generating RTLIL representation for module `\GP_BANDGAP'.
Generating RTLIL representation for module `\GP_COUNT8'.
Generating RTLIL representation for module `\GP_COUNT14'.
Generating RTLIL representation for module `\GP_COUNT8_ADV'.
Generating RTLIL representation for module `\GP_COUNT14_ADV'.
Generating RTLIL representation for module `\GP_DAC'.
Generating RTLIL representation for module `\GP_DELAY'.
Generating RTLIL representation for module `\GP_DFF'.
Generating RTLIL representation for module `\GP_DFFR'.
Generating RTLIL representation for module `\GP_DFFS'.
Generating RTLIL representation for module `\GP_DFFSR'.
Generating RTLIL representation for module `\GP_IBUF'.
Generating RTLIL representation for module `\GP_IOBUF'.
Generating RTLIL representation for module `\GP_INV'.
Generating RTLIL representation for module `\GP_LFOSC'.
Generating RTLIL representation for module `\GP_OBUF'.
Generating RTLIL representation for module `\GP_OBUFT'.
Generating RTLIL representation for module `\GP_PGA'.
Generating RTLIL representation for module `\GP_POR'.
Generating RTLIL representation for module `\GP_RCOSC'.
Generating RTLIL representation for module `\GP_RINGOSC'.
Generating RTLIL representation for module `\GP_SHREG'.
Generating RTLIL representation for module `\GP_SYSRESET'.
Generating RTLIL representation for module `\GP_VDD'.
Generating RTLIL representation for module `\GP_VREF'.
Generating RTLIL representation for module `\GP_VSS'.
Successfully finished Verilog frontend.
2.2. Executing HIERARCHY pass (managing design hierarchy).
2.2.1. Analyzing design hierarchy..
Top module: \top
2.2.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.3. Executing PROC pass (convert processes to netlists).
2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.3.3. Executing PROC_INIT pass (extract init attributes).
2.3.4. Executing PROC_ARST pass (detect async resets in processes).
2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$proc$shift-reg/shift-reg.v:61$1'.
1/1: $0\shift_reg[15:0]
2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).
2.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\shift_reg' using process `\top.$proc$shift-reg/shift-reg.v:61$1'.
created $dff cell `$procdff$2' with positive edge clock.
2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$shift-reg/shift-reg.v:61$1'.
Cleaned up 0 empty switches.
2.4. Executing FLATTEN pass (flatten design).
No more expansions possible.
2.5. Executing TRIBUF pass.
2.6. Executing SYNTH pass.
2.6.1. Executing PROC pass (convert processes to netlists).
2.6.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.6.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.6.1.3. Executing PROC_INIT pass (extract init attributes).
2.6.1.4. Executing PROC_ARST pass (detect async resets in processes).
2.6.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
2.6.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).
2.6.1.7. Executing PROC_DFF pass (convert process syncs to FFs).
2.6.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.6.2. Executing OPT_EXPR pass (perform const folding).
2.6.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.6.4. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
2.6.5. Executing OPT pass (performing simple optimizations).
2.6.5.1. Executing OPT_EXPR pass (perform const folding).
2.6.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.6.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.6.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.6.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.6.5.6. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
2.6.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.6.5.8. Executing OPT_EXPR pass (perform const folding).
2.6.5.9. Finished OPT passes. (There is nothing left to do.)
2.6.6. Executing WREDUCE pass (reducing word size of cells).
2.6.7. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
created 0 $alu and 0 $macc cells.
2.6.8. Executing SHARE pass (SAT-based resource sharing).
2.6.9. Executing OPT pass (performing simple optimizations).
2.6.9.1. Executing OPT_EXPR pass (perform const folding).
2.6.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.6.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.6.9.6. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
2.6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.6.9.8. Executing OPT_EXPR pass (perform const folding).
2.6.9.9. Finished OPT passes. (There is nothing left to do.)
2.6.10. Executing FSM pass (extract and optimize FSM).
2.6.10.1. Executing FSM_DETECT pass (finding FSMs in design).
2.6.10.2. Executing FSM_EXTRACT pass (extracting FSM from design).
2.6.10.3. Executing FSM_OPT pass (simple optimizations of FSMs).
2.6.10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.6.10.5. Executing FSM_OPT pass (simple optimizations of FSMs).
2.6.10.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
2.6.10.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
2.6.10.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
2.6.11. Executing OPT pass (performing simple optimizations).
2.6.11.1. Executing OPT_EXPR pass (perform const folding).
2.6.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.6.11.3. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
2.6.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.6.11.5. Finished fast OPT passes.
2.6.12. Executing MEMORY pass.
2.6.12.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
2.6.12.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.6.12.3. Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).
2.6.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.6.12.5. Executing MEMORY_COLLECT pass (generating $mem cells).
2.6.13. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.7. Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).
2.8. Executing OPT pass (performing simple optimizations).
2.8.1. Executing OPT_EXPR pass (perform const folding).
2.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.8.3. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
2.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.8.5. Finished fast OPT passes.
2.9. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
2.10. Executing OPT pass (performing simple optimizations).
2.10.1. Executing OPT_EXPR pass (perform const folding).
2.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.10.8. Executing OPT_EXPR pass (perform const folding).
2.10.9. Finished OPT passes. (There is nothing left to do.)
2.11. Executing TECHMAP pass (map to technology primitives).
2.11.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
Mapping top.$procdff$2 ($dff) with simplemap.
No more expansions possible.
2.12. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell GP_DFF (noninv, pins=3, area=1.00) is a direct match for cell type $_DFF_P_.
cell GP_DFFR (noninv, pins=4, area=1.00) is a direct match for cell type $_DFF_PN0_.
cell GP_DFFS (noninv, pins=4, area=1.00) is a direct match for cell type $_DFF_PN1_.
create mapping for $_DFF_PP0_ from mapping for $_DFF_PN0_.
create mapping for $_DFF_PP1_ from mapping for $_DFF_PN1_.
create mapping for $_DFF_N_ from mapping for $_DFF_P_.
create mapping for $_DFF_NN0_ from mapping for $_DFF_PN0_.
create mapping for $_DFF_NP0_ from mapping for $_DFF_NN0_.
create mapping for $_DFF_NN1_ from mapping for $_DFF_NN0_.
create mapping for $_DFF_NP1_ from mapping for $_DFF_NN1_.
final dff cell mappings:
$_DFF_P_ _DFF_N_ (.C(~C), .D( D), .Q( Q));
$_DFF_P_ _DFF_P_ (.C( C), .D( D), .Q( Q));
$_DFF_PN0_ _DFF_NN0_ (.C(~C), .D( D), .Q( Q), .R( R));
$_DFF_PN0_ _DFF_NN1_ (.C(~C), .D(~D), .Q(~Q), .R( R));
$_DFF_PN0_ _DFF_NP0_ (.C(~C), .D( D), .Q( Q), .R(~R));
$_DFF_PN0_ _DFF_NP1_ (.C(~C), .D(~D), .Q(~Q), .R(~R));
$_DFF_PN0_ _DFF_PN0_ (.C( C), .D( D), .Q( Q), .R( R));
$_DFF_PN1_ _DFF_PN1_ (.C( C), .D( D), .Q( Q), .R( R));
$_DFF_PN0_ _DFF_PP0_ (.C( C), .D( D), .Q( Q), .R(~R));
$_DFF_PN1_ _DFF_PP1_ (.C( C), .D( D), .Q( Q), .R(~R));
unmapped dff cell: $_DFFSR_NNN_
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
Mapping DFF cells in module `\top':
mapped 16 $_DFF_P_ cells to $_DFF_P_ cells.
2.13. Executing OPT pass (performing simple optimizations).
2.13.1. Executing OPT_EXPR pass (perform const folding).
2.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.13.3. Executing OPT_RMDFF pass (remove dff with constant values).
Replaced 0 DFF cells.
2.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.13.5. Finished fast OPT passes.
2.14. Executing NLUTMAP pass (mapping to constant drivers).
2.14.1. Executing LUT2MUX pass (convert $lut to $_MUX_).
2.14.2. Executing ABC pass (technology mapping using ABC).
2.14.2.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
2.14.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.14.4. Executing LUT2MUX pass (convert $lut to $_MUX_).
2.14.5. Executing ABC pass (technology mapping using ABC).
2.14.5.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
2.14.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.14.7. Executing LUT2MUX pass (convert $lut to $_MUX_).
2.14.8. Executing ABC pass (technology mapping using ABC).
2.14.8.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
2.14.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.14.10. Executing LUT2MUX pass (convert $lut to $_MUX_).
2.14.11. Executing ABC pass (technology mapping using ABC).
2.14.11.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.
2.14.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
2.15. Executing SHREGMAP pass (map shift registers).
Converting top.$auto$simplemap.cc:403:simplemap_dff$48 ... top.$auto$simplemap.cc:403:simplemap_dff$47 to a shift register with depth 2.
Converted 2 dff cells into 1 shift registers.
2.16. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell GP_DFF (noninv, pins=3, area=1.00) is a direct match for cell type $_DFF_P_.
cell GP_DFFR (noninv, pins=4, area=1.00) is a direct match for cell type $_DFF_PN0_.
cell GP_DFFS (noninv, pins=4, area=1.00) is a direct match for cell type $_DFF_PN1_.
create mapping for $_DFF_PP0_ from mapping for $_DFF_PN0_.
create mapping for $_DFF_PP1_ from mapping for $_DFF_PN1_.
create mapping for $_DFF_N_ from mapping for $_DFF_P_.
create mapping for $_DFF_NN0_ from mapping for $_DFF_PN0_.
create mapping for $_DFF_NP0_ from mapping for $_DFF_NN0_.
create mapping for $_DFF_NN1_ from mapping for $_DFF_NN0_.
create mapping for $_DFF_NP1_ from mapping for $_DFF_NN1_.
final dff cell mappings:
GP_DFF _DFF_N_ (.CLK(~C), .D( D), .Q( Q));
GP_DFF _DFF_P_ (.CLK( C), .D( D), .Q( Q));
GP_DFFR _DFF_NN0_ (.CLK(~C), .D( D), .Q( Q), .nRST( R));
GP_DFFR _DFF_NN1_ (.CLK(~C), .D(~D), .Q(~Q), .nRST( R));
GP_DFFR _DFF_NP0_ (.CLK(~C), .D( D), .Q( Q), .nRST(~R));
GP_DFFR _DFF_NP1_ (.CLK(~C), .D(~D), .Q(~Q), .nRST(~R));
GP_DFFR _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .nRST( R));
GP_DFFS _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .nSET( R));
GP_DFFR _DFF_PP0_ (.CLK( C), .D( D), .Q( Q), .nRST(~R));
GP_DFFS _DFF_PP1_ (.CLK( C), .D( D), .Q( Q), .nSET(~R));
unmapped dff cell: $_DFFSR_NNN_
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
unmapped dff cell: $_DFFSR_PNN_
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
Mapping DFF cells in module `\top':
mapped 14 $_DFF_P_ cells to \GP_DFF cells.
2.17. Executing DFFINIT pass (set INIT param on FF cells).
Setting top.$auto$simplemap.cc:403:simplemap_dff$62.INIT (port=Q, net=\shift_reg [15]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$49.INIT (port=Q, net=\shift_reg [2]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$50.INIT (port=Q, net=\shift_reg [3]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$51.INIT (port=Q, net=\shift_reg [4]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$52.INIT (port=Q, net=\shift_reg [5]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$53.INIT (port=Q, net=\shift_reg [6]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$54.INIT (port=Q, net=\shift_reg [7]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$55.INIT (port=Q, net=\shift_reg [8]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$56.INIT (port=Q, net=\shift_reg [9]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$57.INIT (port=Q, net=\shift_reg [10]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$58.INIT (port=Q, net=\shift_reg [11]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$59.INIT (port=Q, net=\shift_reg [12]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$60.INIT (port=Q, net=\shift_reg [13]) to 0'.
Setting top.$auto$simplemap.cc:403:simplemap_dff$61.INIT (port=Q, net=\shift_reg [14]) to 0'.
2.18. Executing DFFINIT pass (set INIT param on FF cells).
2.19. Executing DFFINIT pass (set INIT param on FF cells).
2.20. Executing DFFINIT pass (set INIT param on FF cells).
2.21. Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).
Mapping port top.bit0 using GP_OBUF.
Mapping port top.bit1 using GP_OBUF.
Mapping port top.bit2 using GP_OBUF.
Mapping port top.bit3 using GP_OBUF.
Mapping port top.bit4 using GP_OBUF.
Mapping port top.bit5 using GP_OBUF.
Mapping port top.bit6 using GP_OBUF.
Mapping port top.bit7 using GP_OBUF.
Mapping port top.bit8 using GP_OBUF.
Mapping port top.bit9 using GP_OBUF.
Mapping port top.bita using GP_OBUF.
Mapping port top.bitb using GP_OBUF.
Mapping port top.bitc using GP_OBUF.
Mapping port top.bitd using GP_OBUF.
Mapping port top.bite using GP_OBUF.
Mapping port top.bitf using GP_OBUF.
Mapping port top.clk using GP_IBUF.
Mapping port top.sin using GP_IBUF.
2.22. Executing ATTRMVCP pass (move or copy attributes).
Moving attribute src="shift-reg/shift-reg.v:39" from top.bitf to top.$auto$iopadmap.cc:330:execute$99.
Moving attribute src="shift-reg/shift-reg.v:38" from top.bite to top.$auto$iopadmap.cc:330:execute$97.
Moving attribute src="shift-reg/shift-reg.v:37" from top.bitd to top.$auto$iopadmap.cc:330:execute$95.
Moving attribute src="shift-reg/shift-reg.v:36" from top.bitc to top.$auto$iopadmap.cc:330:execute$93.
Moving attribute src="shift-reg/shift-reg.v:35" from top.bitb to top.$auto$iopadmap.cc:330:execute$91.
Moving attribute src="shift-reg/shift-reg.v:34" from top.bita to top.$auto$iopadmap.cc:330:execute$89.
Moving attribute src="shift-reg/shift-reg.v:33" from top.bit9 to top.$auto$iopadmap.cc:330:execute$87.
Moving attribute src="shift-reg/shift-reg.v:32" from top.bit8 to top.$auto$iopadmap.cc:330:execute$85.
Moving attribute src="shift-reg/shift-reg.v:31" from top.bit7 to top.$auto$iopadmap.cc:330:execute$83.
Moving attribute src="shift-reg/shift-reg.v:30" from top.bit6 to top.$auto$iopadmap.cc:330:execute$81.
Moving attribute src="shift-reg/shift-reg.v:29" from top.bit5 to top.$auto$iopadmap.cc:330:execute$79.
Moving attribute src="shift-reg/shift-reg.v:28" from top.bit4 to top.$auto$iopadmap.cc:330:execute$77.
Moving attribute src="shift-reg/shift-reg.v:27" from top.bit3 to top.$auto$iopadmap.cc:330:execute$75.
Moving attribute src="shift-reg/shift-reg.v:26" from top.bit2 to top.$auto$iopadmap.cc:330:execute$73.
Moving attribute src="shift-reg/shift-reg.v:25" from top.bit1 to top.$auto$iopadmap.cc:330:execute$71.
Moving attribute src="shift-reg/shift-reg.v:24" from top.bit0 to top.$auto$iopadmap.cc:330:execute$69.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$shregmap.cc:77:fixup$67.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$shregmap.cc:77:fixup$67.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$49.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$50.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$51.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$52.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$53.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$54.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$55.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$56.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$57.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$58.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$59.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$60.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$61.
Moving attribute src="shift-reg/shift-reg.v:41" from top.shift_reg to top.$auto$simplemap.cc:403:simplemap_dff$62.
2.23. Executing ATTRMVCP pass (move or copy attributes).
Moving attribute src="shift-reg/shift-reg.v:23" from top.sin to top.$auto$iopadmap.cc:330:execute$103.
Moving attribute src="shift-reg/shift-reg.v:22" from top.clk to top.$auto$iopadmap.cc:330:execute$101.
2.24. Executing TECHMAP pass (map to technology primitives).
2.24.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/greenpak4/cells_map.v' to AST representation.
Generating RTLIL representation for module `\GP_DFFS'.
Generating RTLIL representation for module `\GP_DFFR'.
Generating RTLIL representation for module `\GP_OBUFT'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
No more expansions possible.
Removed 0 unused cells and 16 unused wires.
2.25. Executing HIERARCHY pass (managing design hierarchy).
2.25.1. Analyzing design hierarchy..
Top module: \top
2.25.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.26. Printing statistics.
=== top ===
Number of wires: 21
Number of wire bits: 36
Number of public wires: 19
Number of public wire bits: 34
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 33
GP_DFF 14
GP_IBUF 2
GP_OBUF 16
GP_SHREG 1
2.27. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
-- Writing to `shift-reg/shift-reg.json' using backend `json' --
. Executing JSON backend.
End of script. Logfile hash: 8053113822
CPU: user 0.96s system 0.08s, MEM: 11.11 MB total, 4.61 MB resident
Yosys 0.6+193 (git sha1 0515809, gcc 4.8.4-2ubuntu1~14.04.3 -fPIC -Os)
Time spent: 28% 1x share (0 sec), 16% 5x read_verilog (0 sec), ...
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