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cr1901/top.srp

Last active February 10, 2017 21:39
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So... what's the actual period?
Raw
top.srp
Timing Summary:
---------------
Speed Grade: -2
Minimum period: 22.267ns (Maximum Frequency: 44.909MHz)
Minimum input arrival time before clock: 2.083ns
Maximum output required time after clock: 5.996ns
Maximum combinational path delay: 1.328ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk100'
Clock period: 22.267ns (frequency: 44.909MHz)
Total number of paths / destination ports: 291857 / 6982
-------------------------------------------------------------------------
Delay: 13.917ns (Levels of Logic = 1)
Source: lm32_cpu/multiplier/Mmult_n0023 (DSP)
Destination: lm32_cpu/multiplier/Mmult_n00232 (DSP)
Source Clock: clk100 rising 1.6X
Destination Clock: clk100 rising 1.6X
Data Path: lm32_cpu/multiplier/Mmult_n0023 to lm32_cpu/multiplier/Mmult_n00232
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
DSP48A1:CLK->P47 18 7.889 1.234 lm32_cpu/multiplier/Mmult_n0023 (lm32_cpu/multiplier/Mmult_n0023_P47_to_Mmult_n00231)
DSP48A1:C30->PCOUT47 1 3.149 0.000 lm32_cpu/multiplier/Mmult_n00231 (lm32_cpu/multiplier/Mmult_n00231_PCOUT_to_Mmult_n00232_PCIN_47)
DSP48A1:PCIN47 1.645 lm32_cpu/multiplier/Mmult_n00232
----------------------------------------
Total 13.917ns (12.683ns logic, 1.234ns route)
(91.1% logic, 8.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'jt51/p1'
Clock period: 17.563ns (frequency: 56.937MHz)
Total number of paths / destination ports: 6415498 / 2482
-------------------------------------------------------------------------
Delay: 17.563ns (Levels of Logic = 21)
Source: jt51/u_eg/eg_out_VI_4 (FF)
Destination: jt51/u_eg/eg_in_9 (FF)
Source Clock: jt51/p1 rising
Destination Clock: jt51/p1 rising
Data Path: jt51/u_eg/eg_out_VI_4 to jt51/u_eg/eg_in_9
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 29 0.525 1.900 jt51/u_eg/eg_out_VI_4 (jt51/u_eg/eg_out_VI_4)
LUT6:I1->O 2 0.254 0.954 jt51/u_eg/Mmux_ar_sum6211 (jt51/u_eg/Mmux_ar_sum621)
LUT4:I1->O 1 0.235 0.790 jt51/u_eg/Mmux_ar_sum72 (jt51/u_eg/Mmux_ar_sum71)
LUT6:I4->O 1 0.250 0.682 jt51/u_eg/Mmux_ar_sum73 (jt51/u_eg/Mmux_ar_sum72)
LUT5:I4->O 3 0.254 0.994 jt51/u_eg/Mmux_ar_sum75 (jt51/u_eg/ar_sum<6>)
LUT4:I1->O 1 0.235 0.000 jt51/u_eg/Mcompar_ar_sum[9]_eg_out_VI[9]_LessThan_48_o_lut<3> (jt51/u_eg/Mcompar_ar_sum[9]_eg_out_VI[9]_LessThan_48_o_lut<3>)
MUXCY:S->O 1 0.427 0.910 jt51/u_eg/Mcompar_ar_sum[9]_eg_out_VI[9]_LessThan_48_o_cy<3> (jt51/u_eg/Mcompar_ar_sum[9]_eg_out_VI[9]_LessThan_48_o_cy<3>)
LUT5:I2->O 15 0.235 1.431 jt51/u_eg/Mcompar_ar_sum[9]_eg_out_VI[9]_LessThan_48_o_cy<4> (jt51/u_eg/Mcompar_ar_sum[9]_eg_out_VI[9]_LessThan_48_o_cy<4>)
LUT4:I0->O 14 0.254 1.403 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_B1121 (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_B112)
LUT6:I2->O 1 0.254 1.137 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_B33 (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_B33)
LUT6:I0->O 1 0.254 1.112 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_B36 (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_B36)
LUT6:I1->O 1 0.254 0.910 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_B37 (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_B<2>)
LUT5:I2->O 1 0.235 0.000 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_lut<2> (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_lut<2>)
MUXCY:S->O 1 0.215 0.000 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<2> (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<2>)
MUXCY:CI->O 1 0.023 0.000 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<3> (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<3>)
MUXCY:CI->O 1 0.023 0.000 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<4> (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<4>)
MUXCY:CI->O 1 0.023 0.000 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<5> (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<5>)
MUXCY:CI->O 1 0.023 0.000 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<6> (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<6>)
MUXCY:CI->O 1 0.023 0.000 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<7> (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<7>)
MUXCY:CI->O 0 0.023 0.000 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<8> (jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_cy<8>)
XORCY:CI->O 1 0.206 0.790 jt51/u_eg/Mmux_eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT_rs_xor<9> (jt51/u_eg/eg_out_VI[9]_eg_out_VI[9]_mux_92_OUT<9>)
LUT4:I2->O 1 0.250 0.000 jt51/u_eg/eg_in_9_glue_set (jt51/u_eg/eg_in_9_glue_set)
FDR:D 0.074 jt51/u_eg/eg_in_9
----------------------------------------
Total 17.563ns (4.550ns logic, 13.013ns route)
(25.9% logic, 74.1% route)
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