Migen Case Bug?

case.py

from migen import *
from migen.fhdl import verilog

class CaseTest(Module):
    def __init__(self):
        self.a = Signal(1)
        self.b = Signal(1)
        self.choose = Signal(1)
        self.o = Signal(1)
        
        case_index = [self.a, self.b]
        act = dict((i, self.o.eq(case_index[i])) for i in range(2))
        
        self.comb += [Case(self.choose, act)]
        
print(verilog.convert(CaseTest()))