Migen Simulation with manually-specified clock domain

sim_cd.py

from migen.fhdl.std import *
from migen.sim.generic import run_simulation, Simulator, TopLevel
from migen.sim.icarus import Runner

# Suppose this is the module I'm interested in seeing the output of:
class CounterWithReset(Module):
    def __init__(self):
        self.counter = Signal(32)
        self.reset = Signal(1)
        self.clock_domains.slow = ClockDomain()
        
        ###
        
        self.sync.slow += [If(self.reset, self.counter.eq(0)),
            self.counter.eq(self.counter + 1)]
            
    def do_simulation(self, selfp):
        pass # Do stuff here.
        
# Both these will bomb with "Unable to bind"... slow/sys_clk/reset was decorated
# with another name- slow/sys_clk_1/reset_1!
try:
    with Simulator(ClockDomainsRenamer({"slow" : "sys"})(CounterWithReset()),
        TopLevel(vcd_name="cd.vcd", top_name="top_sys",
            dut_type="dut_sys", dut_name="dut_sys"),
        Runner(keep_files=True, top_file="migensim_top_sys.v",
            dut_file="migensim_dut_sys.v")) as s:
            s.run(20)
except Exception:
    pass

try:
    with Simulator(ClockDomainsRenamer({"sys" : "slow"})(CounterWithReset()),
        TopLevel(vcd_name="cd.vcd", cd_name="slow", top_name="top_slow",
            dut_type="dut_slow", dut_name="dut_slow"),
        Runner(keep_files=True, top_file="migensim_top_slow.v",
            dut_file="migensim_dut_slow.v")) as s:
            s.run(20)
except Exception:
    pass