MiSoC Freq Counters

build.hint

make BOARD=minispartan6 TARGET=base MISOC_EXTRA_CMDLINE="-sFreqSoC -Ob source True -Ob run False" gateware

freq_count.py

from migen.fhdl.std import *
from migen.genlib.fifo import AsyncFIFO
from migen.fhdl.bitcontainer import flen
from migen.bank.description import *


# Allocate room for 3 frequency counters.
class FreqCounterDebug(Module, AutoCSR):
    def __init__(self, counter_param_list):
        for params in counter_param_list:
            self.submodules += FreqCounter(*params)
        

class FreqCounter(Module, AutoCSR):
    # measured_sig: Signal to measure frequency
    # ref_clk: counts up to a gate_time number of cycles. It should be at least 
    # twice as fast as the maximum frequency of the measured signal to avoid
    # samples being missed.
    # self.freq_out is the last measured frequency over the interval.
    # posedge: If true, edge transitions from low to high count as a frequency event.
    # Otherwise, high to low transitions count.
    def __init__(self, measured_sig, ref_clk, gate_time=50000000, posedge=True):
        self.clock_domains.cd_ref_clk = ClockDomain()
        self.comb += [self.cd_ref_clk.clk.eq(ref_clk)]

        event = Signal(1)
        prev_sig = Signal(1)
        gate_count = Signal(max=gate_time)
        freq_count = Signal(max=gate_time)
        self.freq_out = CSRStatus(32)

        self.sync.ref_clk += [prev_sig.eq(measured_sig)]
        
        if posedge:
            self.comb += [event.eq(measured_sig & ~prev_sig)]
        else:
            self.comb += [event.eq(~measured_sig & prev_sig)]

        # We will latch data into the queue on the leading edge of the next
        # clock if gate_count has saturated.
        self.sync.ref_clk += [If(gate_count == gate_time - 1,
                gate_count.eq(0),
                freq_count.eq(0),
                self.freq_out.status.eq(freq_count)).
            Else(
                # TODO: We should probably count an edge transition detected
                # on the leading edge just before the gate_count resets.
                If(event,
                    freq_count.eq(freq_count + 1))
                )]

minispartan6_base.py

from fractions import Fraction

from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.actorlib.fifo import SyncFIFO

from misoclib.mem.sdram.module import AS4C16M16
from misoclib.mem.sdram.phy import gensdrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.soc.sdram import SDRAMSoC

from liteusb.common import *
from liteusb.phy.ft245 import FT245PHY
from liteusb.core import LiteUSBCore
from liteusb.frontend.uart import LiteUSBUART
from liteusb.frontend.wishbone import LiteUSBWishboneBridge

from misoclib.com.gpio import GPIOOut

# Debug stuff
from gateware.freq_count import FreqCounterDebug
from migen.genlib.misc import Counter

class _CRG(Module):
    def __init__(self, platform, clk_freq):
        self.clock_domains.cd_sys = ClockDomain()
        self.clock_domains.cd_sys_ps = ClockDomain()

        f0 = 32*1000000
        clk32 = platform.request("clk32")
        clk32a = Signal()
        self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
        clk32b = Signal()
        self.specials += Instance("BUFIO2", p_DIVIDE=1,
                                  p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
                                  i_I=clk32a, o_DIVCLK=clk32b)
        f = Fraction(int(clk_freq), int(f0))
        n, m, p = f.denominator, f.numerator, 8
        assert f0/n*m == clk_freq
        pll_lckd = Signal()
        pll_fb = Signal()
        pll = Signal(6)
        self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
                                     p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
                                     p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
                                     i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
                                     p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
                                     i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
                                     p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
                                     i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
                                     o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
                                     o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
                                     o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
                                     o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
                                     o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
                                     o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
                                     p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
                                     p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
                                     p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
                                     p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
                                     p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,  # sys
                                     p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1,  # sys_ps
        )
        self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
        self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
        self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)

        self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
                                  p_INIT=0, p_SRTYPE="SYNC",
                                  i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
                                  i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
                                  o_Q=platform.request("sdram_clock"))


class BaseSoC(SDRAMSoC):
    default_platform = "minispartan6"

    def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
        clk_freq = 80*1000000
        SDRAMSoC.__init__(self, platform, clk_freq,
                          integrated_rom_size=0x8000,
                          sdram_controller_settings=sdram_controller_settings,
                          **kwargs)

        self.submodules.crg = _CRG(platform, clk_freq)

        if not self.integrated_main_ram_size:
            self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
                                                         AS4C16M16(clk_freq))
            self.register_sdram_phy(self.sdrphy)




# Test SoC for frequency counters.
class FreqSoC(BaseSoC):
    csr_map = {
        "freq_counters": 16,
    }
    csr_map.update(BaseSoC.csr_map)
    
    def __init__(self, platform, **kwargs):
        BaseSoC.__init__(self, platform, **kwargs)
        
        # Create a clock domain to play with- get some generate signals from here.
        clk50 = platform.request("clk50")
        self.clock_domains.cd_clk50 = ClockDomain()
        self.comb += self.cd_clk50.clk.eq(clk50)
        
        # 25 MHz out-of-phase signal
        test_sig25 = Signal(1)
        self.sync.clk50 += [test_sig25.eq(~test_sig25)]
        
        self.submodules.freq_counters = FreqCounterDebug(
            [(test_sig25, ClockSignal("sys"), 80000000)])
            
        
        

class USBSoC(BaseSoC):
    csr_map = {
        "usb_dma": 16,
    }
    csr_map.update(BaseSoC.csr_map)

    usb_map = {
        "uart":   0,
        "dma":    1,
        "bridge": 2
    }

    def __init__(self, platform, **kwargs):
        BaseSoC.__init__(self, platform, with_uart=False, **kwargs)

        self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
        self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)

        # UART
        usb_uart_port = self.usb_core.crossbar.get_port(self.usb_map["uart"])
        self.submodules.uart = LiteUSBUART(usb_uart_port)

        # DMA
        usb_dma_port = self.usb_core.crossbar.get_port(self.usb_map["dma"])
        usb_dma_loopback_fifo = SyncFIFO(user_description(8), 1024, buffered=True)
        self.submodules += usb_dma_loopback_fifo
        self.comb += [
            usb_dma_port.source.connect(usb_dma_loopback_fifo.sink),
            usb_dma_loopback_fifo.source.connect(usb_dma_port.sink)
        ]

        # Wishbone Bridge
        usb_bridge_port = self.usb_core.crossbar.get_port(self.usb_map["bridge"])
        usb_bridge = LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq)
        self.submodules += usb_bridge
        self.add_wb_master(usb_bridge.wishbone)

        # Leds
        leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
        self.submodules.leds = GPIOOut(leds)

default_subtarget = BaseSoC