Migen Names

names.py

from migen.fhdl.std import *
from migen.fhdl import verilog

class ModB(Module):
    def __init__(self):
        self.out_b = Signal()

        ###
        
        self.sync += [self.out_b.eq(~self.out_b)]


class ModA(Module):
    def __init__(self):
        self.out_a = Signal()
        self.clock_domains.cd_mod_a = ClockDomain()
        
        ###
        
        self.sync.mod_a += [self.out_a.eq(~self.out_a)]
        

class ModTop(Module):
    def __init__(self, input_module):
        self.out_top = Signal()
        self.submodules.mod_b = ModB()
        self.submodules.mod_a = input_module
        self.clock_domains.sys = ClockDomain("sys")
        
        ###
        
        self.sync += [self.out_top.eq(~self.out_top)]


m = ModTop(ModA())
print(verilog.convert(m, {m.sys.clk, m.sys.rst, m.mod_a.cd_mod_a.clk}))

names.v

/* Machine-generated using Migen */
module top(
	input mod_a_clk,
	input sys_clk,
	input sys_rst
);

reg moda_out_a = 1'd0;
reg mod_a_rst = 1'd0;
reg __main___out_top = 1'd0;
reg __main___out_b = 1'd0;


always @(posedge mod_a_clk) begin
	if (mod_a_rst) begin
		moda_out_a <= 1'd0;
	end else begin
		moda_out_a <= (~moda_out_a);
	end
end

always @(posedge sys_clk) begin
	if (sys_rst) begin
		__main___out_top <= 1'd0;
		__main___out_b <= 1'd0;
	end else begin
		__main___out_top <= (~__main___out_top);
		__main___out_b <= (~__main___out_b);
	end
end

endmodule

names_no_cd.py

from migen.fhdl.std import *
from migen.fhdl import verilog

class ModB(Module):
    def __init__(self):
        self.out_b = Signal()

        ###
        
        self.sync += [self.out_b.eq(~self.out_b)]


class ModA(Module):
    def __init__(self):
        self.out_a = Signal()
        # self.clock_domains.cd_mod_a = ClockDomain()
        
        ###
        
        # self.sync.mod_a += [self.out_a.eq(~self.out_a)]
        self.sync += [self.out_a.eq(~self.out_a)]
        

class ModTop(Module):
    def __init__(self, input_module):
        self.out_top = Signal()
        self.submodules.mod_b = ModB()
        self.submodules.mod_a = input_module
        # self.clock_domains.sys = ClockDomain("sys")
        
        ###
        
        self.sync += [self.out_top.eq(~self.out_top)]


m = ModTop(ModA())
print(verilog.convert(m))

names_no_cd.v

/* Machine-generated using Migen */
module top(
	input sys_clk,
	input sys_rst
);

reg out_a = 1'd0;
reg out_top = 1'd0;
reg out_b = 1'd0;


always @(posedge sys_clk) begin
	if (sys_rst) begin
		out_a <= 1'd0;
		out_top <= 1'd0;
		out_b <= 1'd0;
	end else begin
		out_top <= (~out_top);
		out_b <= (~out_b);
		out_a <= (~out_a);
	end
end

endmodule