Migen Verilog Generation Error

errors.txt

Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> WARNING:Xst:1583 - You are using an internal switch '-use_new_parser'.
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Input Format                       : MIXED

---- Target Parameters
Output File Name                   : "top.ngc"
Target Device                      : xc3s200a-4-vq100

---- Source Options
Top Module Name                    : top
Use New Parser                     : yes
Automatic Register Balancing       : yes

---- General Options
Optimization Goal                  : AREA

=========================================================================

WARNING:Xst:29 - Optimization Effort not specified
=========================================================================

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "C:\msys64\home\William\src\migen_mercury\sram\top.v" into library work
Parsing module <top>.
ERROR:HDLCompiler:806 - "C:\msys64\home\William\src\migen_mercury\sram\top.v" Line 38: Syntax error near "[".
ERROR:HDLCompiler:598 - "C:\msys64\home\William\src\migen_mercury\sram\top.v" Line 2: Module <top> ignored due to previous errors.
Verilog file C:\msys64\home\William\src\migen_mercury\sram\top.v ignored due to errors
--> 

Total memory usage is 182912 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    0 (   0 filtered)

mercury.py

# This file is Copyright (c) 2015 William D. Jones <[email protected]>
# License: BSD

from mibuild.generic_platform import *
from mibuild.xilinx import XilinxPlatform
from mibuild.xilinx.programmer import XC3SProg

_io = [
   ("clk", 0, Pins("P43"), IOStandard("LVCMOS33")),	

   ("user_led", 0, Pins("P13"), IOStandard("LVTTL")),
   ("user_led", 1, Pins("P15"), IOStandard("LVTTL")),
   ("user_led", 2, Pins("P16"), IOStandard("LVTTL")),
   ("user_led", 3, Pins("P19"), IOStandard("LVTTL")),
   ("user_btn", 0, Pins("P41"), IOStandard("LVTTL")),
   
   
   #The serial port is in fact over SPI. The creators of the board provide a VHDL
   #file for talking over this interface. In light of space constraints and the fact
   #that both the FT245RL and FPGA can BOTH be SPI primaries, however,
   #It may be necessary to sacrifice two "high-speed" (DIO, INPIN) pins instead.
   ("serial", 0,
        Subsignal("tx", Pins("P20"), IOStandard("LVCMOS33")),  # FTDI D1
        Subsignal("rx", Pins("P68"), IOStandard("LVCMOS33"))   # FTDI D0
   ),
   
   #The FPGA is simultaneously an SPI primary and secondary!
   #FPGA is secondary...
   #("spiserial", 0,
   #	#Subsignal("fpga_prog", Pins("V3"), IOStandard("LVTTL"))
   #     Subsignal("fpga_csn", Pins("P39"), IOStandard("LVTTL")),
   #     Subsignal("clk", Pins("P53"), IOStandard("LVTTL")),
   #     Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")),
   #     Subsignal("miso", Pins("P51"), IOStandard("LVTTL"))
   # ),
   
   
   #FPGA is primary...
   ("spiflash", 0,
        Subsignal("flash_csn", Pins("P27"), IOStandard("LVTTL")),
        Subsignal("clk", Pins("P53"), IOStandard("LVTTL")),
        Subsignal("mosi", Pins("P46"), IOStandard("LVTTL")),
        Subsignal("miso", Pins("P51"), IOStandard("LVTTL"))
    ),
   ("spiflash2x", 0,
        Subsignal("cs_n", Pins("P27")),
        Subsignal("clk", Pins("P53")),
        Subsignal("dq", Pins("P46", "P51")),
        IOStandard("LVTTL"), Misc("SLEW=FAST")
    ),
   
   #SRAM and 5V-tolerant I/O share a parallel bus. The SRAM controller needs
   #to take care of switching the bus between the two.
   ("gpio_sram_bus", 0,
        Subsignal("a", Pins("P59 P60 P61 P62 P64 P57 P56 P52 P50 P49 P85 P84"
        	            "P83 P78 P77 P65 P70 P71 P72 P73")), #A19 is actually unused.
        Subsignal("d", Pins("P5 P4 P6 P98 P94 P93 P90 P89")), #8-bit data bus
        Subsignal("we_n", Pins("P88")),
        Subsignal("unused", Pins("P86")),
        #Subsignal("oe_n", Pins()), #If OE wasn't tied to ground on Mercury, this pin would be here.
        Subsignal("ce_n", Pins("P59")), #Memory chip-enable. Called MEM_CEN in schematic.
        Subsignal("bussw_oe_n", Pins("P60")), #Mercury-specific. 5V tolerant GPIO is shared w/ memory using this pin.
        IOStandard("LVTTL"), Misc("SLEW=FAST")
    ),
   
   #ADC over SPI- FPGA is primary
   ("adc", 0,
        Subsignal("cs_n", Pins("P21"), IOStandard("LVTTL")),
        Subsignal("clk",  Pins("P10"), IOStandard("LVTTL")),
        Subsignal("mosi", Pins("P9" ), IOStandard("LVTTL")),
        Subsignal("miso", Pins("P12"), IOStandard("LVTTL"))
    )
]

#Perhaps define some connectors as having a specific purpose- i.e. a 5V GPIO bus
#with data, peripheral-select, and control signals?
_connectors = []
"""_connectors = [
    ("IO", "P59 P60 P61 P62 P64 P57 P56 P52 P50 P49 P85 P84 P83 P78 P77 P65 P70" 
    	   "P71 P72 P73 P5 P4 P6 P98 P94 P93 P90 P89 P88 P86"), #5V I/O
    ("DIO", "P20 P32 P33 P34 P35 P36 P37"), #Fast 3.3V IO (Directly attached to FPGA)
    ("CIO", "P40 P44"), #Clock IO
    ("INPIN", "P68 P97 P7 P82")	 #Input-only pins   
]"""

class Platform(XilinxPlatform):
    default_clk_name = "clk"
    default_clk_period = 20

    def __init__(self, device="xc3s200a-4-vq100", programmer="xc3sprog"):
        self.programmer = programmer
        XilinxPlatform.__init__(self, device, _io, _connectors)
        #Small device- optimize for AREA instead of speed (LM32 runs at about 
        #65MHz in AREA configuration).
        self.toolchain.xst_opt = self.toolchain.xst_opt.replace("SPEED", "AREA")
        
    def create_programmer(self):
        #Not actually supported right now- I need to add FT245RL support to xc3sprog.
        if self.programmer == "xc3sprog":
            return XC3SProg("mercury", "bscan_spi_mercury.bit")
        else:
            raise ValueError("{} programmer is not supported".format(programmer))

sram.py

from migen.fhdl.std import *
from migen.genlib.io import *
from mibuild.platforms import mercury


class GPIOSRAMMux(Module):
    def __init__(self, pads):
        #Unified input interface- use mem_cen and bussw to figure out the source.
        self.input_bus = Signal(30)
        
        #GPIO interface- output
        self.gpio_out = Signal(30)
        
        #SRAM interface- output/input
        self.sram_addr = Signal(19) #Output only
        self.sram_data = Signal(8) #Bidirectional- Mux with GPIO input [20:27] as well!
        self.sram_cen = Signal(1) #Output only
        self.sram_wen = Signal(1) #Output only
        
        ###
        self.pins = pads.raw_bits() #Concatenate the subsignals of shared SRAM/GPIO into one
        self.into_fpga = Signal(30) #Create the input bus from the FPGA pins
        self.out_of_fpga = Signal(30) #The output bus to the FPGA pins
        self.per_pin_oe = Signal(30) #Output enable for FPGA pins
        self.iobufs = [TSTriple() for i in range(30)] #Initialize tristates
        
        #Do single pin to test.
        for i in range(1):
            self.comb += [self.into_fpga[i].eq(self.iobufs[i].i)]
            self.comb += [self.iobufs[i].o.eq(self.out_of_fpga[i])]
            self.comb += [self.iobufs[i].oe.eq(self.per_pin_oe[i])]
            self.specials += [self.iobufs[i].get_tristate(self.pins[i])]


"""("gpio_sram_bus", 0,
        Subsignal("a", Pins("P59 P60 P61 P62 P64 P57 P56 P52 P50 P49 P85 P84"
        	            "P83 P78 P77 P65 P70 P71 P72 P73")), #A19 is actually unused.
        Subsignal("d", Pins("P5 P4 P6 P98 P94 P93 P90 P89")), #8-bit data bus
        Subsignal("we_n", Pins("P88")),
        Subsignal("unused", Pins("P86")),
        #Subsignal("oe_n", Pins()), #If OE wasn't tied to ground on Mercury, this pin would be here.
        Subsignal("ce_n", Pins("P59")), #Memory chip-enable. Called MEM_CEN in schematic.
        Subsignal("bussw_oe_n", Pins("P60")), #Mercury-specific. 5V tolerant GPIO is shared w/ memory using this pin.
        IOStandard("LVTTL"), Misc("SLEW=FAST")
    )"""


plat = mercury.Platform()
sram_bus = plat.request("gpio_sram_bus")
m = Module()
m.submodules += GPIOSRAMMux(sram_bus)
#clk = plat.request("clk")

plat.build_cmdline(m, source=True, run=True, build_dir="sram")

top.v

/* Machine-generated using Migen */
module top(
	inout [18:0] gpio_sram_bus_a,
	inout [7:0] gpio_sram_bus_d,
	inout gpio_sram_bus_we_n,
	inout gpio_sram_bus_unused,
	inout gpio_sram_bus_ce_n,
	inout gpio_sram_bus_bussw_oe_n,
	input clk
);

wire [29:0] into_fpga;
reg [29:0] out_of_fpga = 1'd0;
reg [29:0] per_pin_oe = 1'd0;
wire o;
wire oe;
wire i;
wire sys_clk;
wire sys_rst;
wire por_clk;
reg rst_n = 1'd0;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign into_fpga[0] = i;
assign o = out_of_fpga[0];
assign oe = per_pin_oe[0];
assign sys_clk = clk;
assign por_clk = clk;
assign sys_rst = (~rst_n);

always @(posedge por_clk) begin
	rst_n <= 1'd1;
end

assign {gpio_sram_bus_bussw_oe_n, gpio_sram_bus_ce_n, gpio_sram_bus_unused, gpio_sram_bus_we_n, gpio_sram_bus_d, gpio_sram_bus_a}[0] = oe ? o : 1'bz;
assign i = {gpio_sram_bus_bussw_oe_n, gpio_sram_bus_ce_n, gpio_sram_bus_unused, gpio_sram_bus_we_n, gpio_sram_bus_d, gpio_sram_bus_a}[0];

endmodule