YMSoC platform-independent Verilog

top.v

/* Machine-generated using Migen */
module top(
	output audio_a0,
	output audio_a1,
	output user_led,
	output user_led_1,
	input clk32,
	output serial_tx,
	input serial_rx,
	output user_led_2
);

wire [29:0] ymsoc_ibus_adr;
wire [31:0] ymsoc_ibus_dat_w;
wire [31:0] ymsoc_ibus_dat_r;
wire [3:0] ymsoc_ibus_sel;
wire ymsoc_ibus_cyc;
wire ymsoc_ibus_stb;
wire ymsoc_ibus_ack;
wire ymsoc_ibus_we;
wire [2:0] ymsoc_ibus_cti;
wire [1:0] ymsoc_ibus_bte;
wire ymsoc_ibus_err;
wire [29:0] ymsoc_dbus_adr;
wire [31:0] ymsoc_dbus_dat_w;
wire [31:0] ymsoc_dbus_dat_r;
wire [3:0] ymsoc_dbus_sel;
wire ymsoc_dbus_cyc;
wire ymsoc_dbus_stb;
reg ymsoc_dbus_ack = 1'd0;
wire ymsoc_dbus_we;
wire [2:0] ymsoc_dbus_cti;
wire [1:0] ymsoc_dbus_bte;
reg ymsoc_dbus_err = 1'd0;
wire [31:0] ymsoc_interrupt;
wire [31:0] ymsoc_i_adr_o;
wire [31:0] ymsoc_d_adr_o;
wire [29:0] ymsoc_tmpu_adr;
wire [31:0] ymsoc_tmpu_dat_w;
wire [31:0] ymsoc_tmpu_dat_r;
wire [3:0] ymsoc_tmpu_sel;
wire ymsoc_tmpu_cyc;
wire ymsoc_tmpu_stb;
wire ymsoc_tmpu_ack;
wire ymsoc_tmpu_we;
wire [2:0] ymsoc_tmpu_cti;
wire [1:0] ymsoc_tmpu_bte;
wire ymsoc_tmpu_err;
reg ymsoc_tmpu_enable_null_storage_full = 1'd0;
wire ymsoc_tmpu_enable_null_storage;
reg ymsoc_tmpu_enable_null_re = 1'd0;
reg ymsoc_tmpu_enable_prog_storage_full = 1'd0;
wire ymsoc_tmpu_enable_prog_storage;
reg ymsoc_tmpu_enable_prog_re = 1'd0;
reg [29:0] ymsoc_tmpu_prog_address_storage_full = 30'd0;
wire [17:0] ymsoc_tmpu_prog_address_storage;
reg ymsoc_tmpu_prog_address_re = 1'd0;
reg ymsoc_tmpu_error = 1'd0;
wire [29:0] ymsoc_rom_bus_adr;
wire [31:0] ymsoc_rom_bus_dat_w;
wire [31:0] ymsoc_rom_bus_dat_r;
wire [3:0] ymsoc_rom_bus_sel;
wire ymsoc_rom_bus_cyc;
wire ymsoc_rom_bus_stb;
reg ymsoc_rom_bus_ack = 1'd0;
wire ymsoc_rom_bus_we;
wire [2:0] ymsoc_rom_bus_cti;
wire [1:0] ymsoc_rom_bus_bte;
reg ymsoc_rom_bus_err = 1'd0;
wire [11:0] ymsoc_rom_adr;
wire [31:0] ymsoc_rom_dat_r;
wire [29:0] ymsoc_sram_bus_adr;
wire [31:0] ymsoc_sram_bus_dat_w;
wire [31:0] ymsoc_sram_bus_dat_r;
wire [3:0] ymsoc_sram_bus_sel;
wire ymsoc_sram_bus_cyc;
wire ymsoc_sram_bus_stb;
reg ymsoc_sram_bus_ack = 1'd0;
wire ymsoc_sram_bus_we;
wire [2:0] ymsoc_sram_bus_cti;
wire [1:0] ymsoc_sram_bus_bte;
reg ymsoc_sram_bus_err = 1'd0;
wire [9:0] ymsoc_sram_adr;
wire [31:0] ymsoc_sram_dat_r;
reg [3:0] ymsoc_sram_we = 4'd0;
wire [31:0] ymsoc_sram_dat_w;
reg [13:0] ymsoc_interface_adr = 14'd0;
reg ymsoc_interface_we = 1'd0;
reg [7:0] ymsoc_interface_dat_w = 8'd0;
wire [7:0] ymsoc_interface_dat_r;
wire [29:0] ymsoc_bus_wishbone_adr;
wire [31:0] ymsoc_bus_wishbone_dat_w;
reg [31:0] ymsoc_bus_wishbone_dat_r = 32'd0;
wire [3:0] ymsoc_bus_wishbone_sel;
wire ymsoc_bus_wishbone_cyc;
wire ymsoc_bus_wishbone_stb;
reg ymsoc_bus_wishbone_ack = 1'd0;
wire ymsoc_bus_wishbone_we;
wire [2:0] ymsoc_bus_wishbone_cti;
wire [1:0] ymsoc_bus_wishbone_bte;
reg ymsoc_bus_wishbone_err = 1'd0;
reg [1:0] ymsoc_counter = 2'd0;
wire [29:0] ymsoc_bus_bus_adr;
wire [31:0] ymsoc_bus_bus_dat_w;
wire [31:0] ymsoc_bus_bus_dat_r;
wire [3:0] ymsoc_bus_bus_sel;
wire ymsoc_bus_bus_cyc;
wire ymsoc_bus_bus_stb;
wire ymsoc_bus_bus_ack;
wire ymsoc_bus_bus_we;
wire [2:0] ymsoc_bus_bus_cti;
wire [1:0] ymsoc_bus_bus_bte;
wire ymsoc_bus_bus_err;
wire [29:0] ymsoc_bus_in_adr;
wire [31:0] ymsoc_bus_in_dat_w;
wire [31:0] ymsoc_bus_in_dat_r;
wire [3:0] ymsoc_bus_in_sel;
wire ymsoc_bus_in_cyc;
wire ymsoc_bus_in_stb;
wire ymsoc_bus_in_ack;
wire ymsoc_bus_in_we;
wire [2:0] ymsoc_bus_in_cti;
wire [1:0] ymsoc_bus_in_bte;
wire ymsoc_bus_in_err;
wire [29:0] ymsoc_bus_out_adr;
wire [31:0] ymsoc_bus_out_dat_w;
wire [31:0] ymsoc_bus_out_dat_r;
wire [3:0] ymsoc_bus_out_sel;
wire ymsoc_bus_out_cyc;
wire ymsoc_bus_out_stb;
wire ymsoc_bus_out_ack;
wire ymsoc_bus_out_we;
reg [2:0] ymsoc_bus_out_cti = 3'd0;
reg [1:0] ymsoc_bus_out_bte = 2'd0;
wire ymsoc_bus_out_err;
reg ymsoc_mcyc_prev = 1'd0;
wire ymsoc_mcyc_negedge;
wire ymsoc_cyc_qual;
reg [3:0] ymsoc_cyc_wait_count = 4'd0;
reg ymsoc_mstb_prev = 1'd0;
wire ymsoc_mstb_negedge;
wire ymsoc_stb_qual;
reg [3:0] ymsoc_stb_wait_count = 4'd0;
wire [31:0] ymsoc_bus_in_full;
wire [31:0] ymsoc_bus_out_full;
wire [29:0] ymsoc_wb2151_bus_adr;
wire [31:0] ymsoc_wb2151_bus_dat_w;
wire [31:0] ymsoc_wb2151_bus_dat_r;
wire [3:0] ymsoc_wb2151_bus_sel;
wire ymsoc_wb2151_bus_cyc;
wire ymsoc_wb2151_bus_stb;
reg ymsoc_wb2151_bus_ack = 1'd0;
wire ymsoc_wb2151_bus_we;
wire [2:0] ymsoc_wb2151_bus_cti;
wire [1:0] ymsoc_wb2151_bus_bte;
reg ymsoc_wb2151_bus_err = 1'd0;
wire ymsoc_wb2151_bus_cs_n;
wire ymsoc_wb2151_bus_wr_n;
wire ymsoc_wb2151_bus_a0;
wire [7:0] ymsoc_wb2151_bus_d_in;
wire [7:0] ymsoc_wb2151_bus_d_out;
wire ymsoc_wb2151_bus_irq_n;
wire ymsoc_wb2151_out_ct1;
wire ymsoc_wb2151_out_ct2;
wire ymsoc_wb2151_out_p1;
wire ymsoc_wb2151_out_sample;
wire [15:0] ymsoc_wb2151_out_dacleft;
wire [15:0] ymsoc_wb2151_out_dacright;
wire ymsoc_irq;
wire ymsoc_time_up_status;
wire ymsoc_time_up_pending;
wire ymsoc_time_up_trigger;
reg ymsoc_time_up_clear = 1'd0;
wire ymsoc_sample_ready_status;
reg ymsoc_sample_ready_pending = 1'd0;
wire ymsoc_sample_ready_trigger;
reg ymsoc_sample_ready_clear = 1'd0;
wire ymsoc_status_re;
wire [1:0] ymsoc_status_r;
reg [1:0] ymsoc_status_w = 2'd0;
wire ymsoc_pending_re;
wire [1:0] ymsoc_pending_r;
reg [1:0] ymsoc_pending_w = 2'd0;
reg [1:0] ymsoc_storage_full = 2'd0;
wire [1:0] ymsoc_storage;
reg ymsoc_re = 1'd0;
wire ymsoc_irq_n;
wire ymsoc_sample;
wire [31:0] ymsoc_host_bus_dat_w;
reg [31:0] ymsoc_host_bus_dat_r = 32'd0;
wire [17:0] ymsoc_host_bus_adr;
wire ymsoc_host_bus_wr;
reg ymsoc_host_bus_ack = 1'd0;
reg ymsoc_host_bus_avail = 1'd0;
reg [15:0] ymsoc_rom_port_adr = 16'd0;
reg ymsoc_rom_port_wr = 1'd0;
reg [31:0] ymsoc_rom_port_dat_w = 32'd0;
wire [31:0] ymsoc_rom_port_dat_r;
reg [15:0] ymsoc_reg_bus_adr = 16'd0;
reg ymsoc_reg_bus_wr = 1'd0;
reg [31:0] ymsoc_reg_bus_dat_w = 32'd0;
reg [31:0] ymsoc_reg_bus_dat_r = 32'd0;
reg [31:0] ymsoc_reg_ctl = 32'd1;
reg [15:0] ymsoc_reg_size = 16'd0;
wire ymsoc_cpu_reset;
wire [11:0] ymsoc_adr;
wire [31:0] ymsoc_dat_r;
wire ymsoc_we;
wire [31:0] ymsoc_dat_w;
wire ymsoc_inp_ct1;
wire ymsoc_inp_ct2;
wire ymsoc_inp_p1;
wire ymsoc_inp_sample;
wire [15:0] ymsoc_inp_dacleft;
wire [15:0] ymsoc_inp_dacright;
wire [15:0] ymsoc_deltasigma0_data;
wire ymsoc_deltasigma0_out;
wire [16:0] ymsoc_deltasigma0_delta;
reg [16:0] ymsoc_deltasigma0_sigma = 17'd0;
wire [15:0] ymsoc_deltasigma1_data;
wire ymsoc_deltasigma1_out;
wire [16:0] ymsoc_deltasigma1_delta;
reg [16:0] ymsoc_deltasigma1_sigma = 17'd0;
wire ym2151_clk;
wire ym2151_rst;
wire sys_clk;
wire sys_rst;
wire por_clk;
wire arb_clk;
wire arb_rst;
wire crg_manual_reset;
reg crg_int_rst = 1'd1;
reg crg_ym_clk = 1'd0;
reg [1:0] crg_cnt = 2'd0;
reg [3:0] crg_reset_cnt = 4'd8;
reg [7:0] out_data = 8'd0;
wire [7:0] in_data;
wire tx;
wire rx;
reg wr = 1'd0;
reg rd = 1'd0;
wire tx_empty;
wire rx_empty;
wire tx_ov;
wire rx_ov;
wire sout_load;
wire [7:0] sout_out_data;
wire sout_shift;
reg sout_empty = 1'd1;
reg sout_overrun = 1'd0;
reg [3:0] sout_count = 4'd0;
reg [9:0] sout_reg = 10'd0;
reg sout_tx = 1'd0;
wire sin_rx;
wire sin_shift;
wire sin_take;
reg [7:0] sin_in_data = 8'd0;
wire sin_edge;
reg sin_empty = 1'd1;
reg sin_busy = 1'd0;
reg sin_overrun = 1'd0;
reg sin_sync_rx = 1'd0;
reg [8:0] sin_reg = 9'd0;
reg sin_rx_prev = 1'd0;
reg [3:0] sin_count = 4'd0;
wire out_active;
wire in_active;
reg shift_out_strobe = 1'd0;
reg shift_in_strobe = 1'd0;
reg [8:0] in_counter = 9'd0;
reg [8:0] out_counter = 9'd0;
reg [31:0] bus_dat_w = 32'd0;
wire [31:0] bus_dat_r;
reg [17:0] bus_adr = 18'd0;
reg bus_wr = 1'd0;
wire bus_ack;
wire bus_avail;
reg [7:0] command = 8'd0;
reg [15:0] addr = 16'd0;
reg [31:0] data = 32'd0;
reg addr_word = 1'd0;
reg [1:0] data_word = 2'd0;
wire read;
wire [1:0] addr_space;
reg [2:0] state = 3'd0;
reg [2:0] next_state = 3'd0;
reg [7:0] command_next_value0 = 8'd0;
reg command_next_value_ce0 = 1'd0;
reg [7:0] t_next_value0 = 8'd0;
reg t_next_value_ce0 = 1'd0;
reg addr_word_next_value1 = 1'd0;
reg addr_word_next_value_ce1 = 1'd0;
reg [7:0] f_next_value0 = 8'd0;
reg f_next_value_ce0 = 1'd0;
reg [7:0] t_next_value1 = 8'd0;
reg t_next_value_ce1 = 1'd0;
reg [1:0] data_word_next_value2 = 2'd0;
reg data_word_next_value_ce2 = 1'd0;
reg [7:0] f_next_value1 = 8'd0;
reg f_next_value_ce1 = 1'd0;
reg [7:0] f_t_next_value = 8'd0;
reg f_t_next_value_ce = 1'd0;
reg [7:0] f_f_next_value = 8'd0;
reg f_f_next_value_ce = 1'd0;
wire [29:0] shared_adr;
wire [31:0] shared_dat_w;
wire [31:0] shared_dat_r;
wire [3:0] shared_sel;
wire shared_cyc;
wire shared_stb;
wire shared_ack;
wire shared_we;
wire [2:0] shared_cti;
wire [1:0] shared_bte;
wire shared_err;
wire [1:0] request;
reg grant = 1'd0;
reg [3:0] slave_sel = 4'd0;
reg [3:0] slave_sel_r = 4'd0;
wire [13:0] interface0_adr;
wire interface0_we;
wire [7:0] interface0_dat_w;
reg [7:0] interface0_dat_r = 8'd0;
wire csrbank0_enable_null0_re;
wire csrbank0_enable_null0_r;
wire csrbank0_enable_null0_w;
wire csrbank0_enable_prog0_re;
wire csrbank0_enable_prog0_r;
wire csrbank0_enable_prog0_w;
wire csrbank0_prog_address3_re;
wire [5:0] csrbank0_prog_address3_r;
wire [5:0] csrbank0_prog_address3_w;
wire csrbank0_prog_address2_re;
wire [7:0] csrbank0_prog_address2_r;
wire [7:0] csrbank0_prog_address2_w;
wire csrbank0_prog_address1_re;
wire [7:0] csrbank0_prog_address1_r;
wire [7:0] csrbank0_prog_address1_w;
wire csrbank0_prog_address0_re;
wire [7:0] csrbank0_prog_address0_r;
wire [7:0] csrbank0_prog_address0_w;
wire csrbank0_sel;
wire [13:0] interface1_adr;
wire interface1_we;
wire [7:0] interface1_dat_w;
reg [7:0] interface1_dat_r = 8'd0;
wire csrbank1_ev_enable0_re;
wire [1:0] csrbank1_ev_enable0_r;
wire [1:0] csrbank1_ev_enable0_w;
wire csrbank1_sel;
reg [29:0] array_muxed0 = 30'd0;
reg [31:0] array_muxed1 = 32'd0;
reg [3:0] array_muxed2 = 4'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg [2:0] array_muxed6 = 3'd0;
reg [1:0] array_muxed7 = 2'd0;
(* register_balancing = "no", shreg_extract = "no" *) reg xilinxmultiregimpl0_regs0 = 1'd0;
(* register_balancing = "no", shreg_extract = "no" *) reg xilinxmultiregimpl0_regs1 = 1'd0;
(* register_balancing = "no", shreg_extract = "no" *) reg xilinxmultiregimpl1_regs0 = 1'd0;
(* register_balancing = "no", shreg_extract = "no" *) reg xilinxmultiregimpl1_regs1 = 1'd0;


// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
// to run the combinatorial process once at the beginning.
// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on

assign ymsoc_rom_port_dat_r = ymsoc_dat_r;
assign ymsoc_dat_w = ymsoc_rom_port_dat_w;
assign ymsoc_we = ymsoc_rom_port_wr;
assign ymsoc_adr = ymsoc_rom_port_adr;
assign ymsoc_inp_ct1 = ymsoc_wb2151_out_ct1;
assign ymsoc_inp_ct2 = ymsoc_wb2151_out_ct2;
assign ymsoc_inp_p1 = ymsoc_wb2151_out_p1;
assign ymsoc_inp_sample = ymsoc_wb2151_out_sample;
assign ymsoc_inp_dacleft = ymsoc_wb2151_out_dacleft;
assign ymsoc_inp_dacright = ymsoc_wb2151_out_dacright;
assign user_led = ymsoc_wb2151_out_ct1;
assign user_led_1 = ymsoc_wb2151_out_ct2;
assign crg_manual_reset = ymsoc_cpu_reset;
assign serial_tx = tx;
assign rx = serial_rx;
assign ymsoc_host_bus_dat_w = bus_dat_w;
assign bus_dat_r = ymsoc_host_bus_dat_r;
assign ymsoc_host_bus_adr = bus_adr;
assign ymsoc_host_bus_wr = bus_wr;
assign bus_ack = ymsoc_host_bus_ack;
assign bus_avail = ymsoc_host_bus_avail;
assign user_led_2 = ym2151_rst;
assign ymsoc_interrupt[0] = ymsoc_irq;
assign ymsoc_ibus_adr = ymsoc_i_adr_o[31:2];
assign ymsoc_dbus_adr = ymsoc_d_adr_o[31:2];
assign ymsoc_tmpu_adr = ymsoc_dbus_adr;
assign ymsoc_tmpu_dat_w = ymsoc_dbus_dat_w;
assign ymsoc_dbus_dat_r = ymsoc_tmpu_dat_r;
assign ymsoc_tmpu_sel = ymsoc_dbus_sel;
assign ymsoc_tmpu_cyc = ymsoc_dbus_cyc;
assign ymsoc_tmpu_stb = ymsoc_dbus_stb;
assign ymsoc_tmpu_we = ymsoc_dbus_we;
assign ymsoc_tmpu_cti = ymsoc_dbus_cti;
assign ymsoc_tmpu_bte = ymsoc_dbus_bte;

// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
	ymsoc_dbus_ack <= 1'd0;
	ymsoc_dbus_err <= 1'd0;
	if (ymsoc_tmpu_error) begin
		ymsoc_dbus_ack <= 1'd0;
		ymsoc_dbus_err <= (ymsoc_tmpu_ack | ymsoc_tmpu_err);
	end else begin
		ymsoc_dbus_ack <= ymsoc_tmpu_ack;
		ymsoc_dbus_err <= ymsoc_tmpu_err;
	end
// synthesis translate_off
	dummy_d <= dummy_s;
// synthesis translate_on
end
assign ymsoc_rom_adr = ymsoc_rom_bus_adr[11:0];
assign ymsoc_rom_bus_dat_r = ymsoc_rom_dat_r;

// synthesis translate_off
reg dummy_d_1;
// synthesis translate_on
always @(*) begin
	ymsoc_sram_we <= 4'd0;
	ymsoc_sram_we[0] <= (((ymsoc_sram_bus_cyc & ymsoc_sram_bus_stb) & ymsoc_sram_bus_we) & ymsoc_sram_bus_sel[0]);
	ymsoc_sram_we[1] <= (((ymsoc_sram_bus_cyc & ymsoc_sram_bus_stb) & ymsoc_sram_bus_we) & ymsoc_sram_bus_sel[1]);
	ymsoc_sram_we[2] <= (((ymsoc_sram_bus_cyc & ymsoc_sram_bus_stb) & ymsoc_sram_bus_we) & ymsoc_sram_bus_sel[2]);
	ymsoc_sram_we[3] <= (((ymsoc_sram_bus_cyc & ymsoc_sram_bus_stb) & ymsoc_sram_bus_we) & ymsoc_sram_bus_sel[3]);
// synthesis translate_off
	dummy_d_1 <= dummy_s;
// synthesis translate_on
end
assign ymsoc_sram_adr = ymsoc_sram_bus_adr[9:0];
assign ymsoc_sram_bus_dat_r = ymsoc_sram_dat_r;
assign ymsoc_sram_dat_w = ymsoc_sram_bus_dat_w;
assign ymsoc_time_up_trigger = (ymsoc_irq_n == 1'd0);
assign ymsoc_sample_ready_trigger = ymsoc_sample;
assign ymsoc_bus_in_full = {ymsoc_bus_in_adr, 2'd0};
assign ymsoc_bus_out_adr = ymsoc_bus_out_full[31:2];
assign ymsoc_cyc_qual = (ymsoc_bus_in_cyc & (ymsoc_cyc_wait_count == 1'd0));
assign ymsoc_stb_qual = (ymsoc_bus_in_stb & (ymsoc_stb_wait_count == 1'd0));
assign ymsoc_mcyc_negedge = ((~ymsoc_bus_in_cyc) & ymsoc_mcyc_prev);
assign ymsoc_mstb_negedge = ((~ymsoc_bus_in_stb) & ymsoc_mstb_prev);
assign ymsoc_wb2151_bus_d_in = ymsoc_wb2151_bus_dat_w[7:0];
assign ymsoc_wb2151_bus_dat_r = {4{ymsoc_wb2151_bus_d_out}};
assign ymsoc_wb2151_bus_a0 = ymsoc_wb2151_bus_adr[0];
assign ymsoc_wb2151_bus_cs_n = (~(ymsoc_wb2151_bus_stb & ymsoc_wb2151_bus_cyc));
assign ymsoc_wb2151_bus_wr_n = (~ymsoc_wb2151_bus_we);
assign ymsoc_bus_in_adr = ymsoc_bus_bus_adr;
assign ymsoc_bus_in_dat_w = ymsoc_bus_bus_dat_w;
assign ymsoc_bus_bus_dat_r = ymsoc_bus_in_dat_r;
assign ymsoc_bus_in_sel = ymsoc_bus_bus_sel;
assign ymsoc_bus_in_cyc = ymsoc_bus_bus_cyc;
assign ymsoc_bus_in_stb = ymsoc_bus_bus_stb;
assign ymsoc_bus_bus_ack = ymsoc_bus_in_ack;
assign ymsoc_bus_in_we = ymsoc_bus_bus_we;
assign ymsoc_bus_in_cti = ymsoc_bus_bus_cti;
assign ymsoc_bus_in_bte = ymsoc_bus_bus_bte;
assign ymsoc_bus_bus_err = ymsoc_bus_in_err;
assign ymsoc_wb2151_bus_adr = ymsoc_bus_out_adr;
assign ymsoc_wb2151_bus_dat_w = ymsoc_bus_out_dat_w;
assign ymsoc_bus_out_dat_r = ymsoc_wb2151_bus_dat_r;
assign ymsoc_wb2151_bus_sel = ymsoc_bus_out_sel;
assign ymsoc_wb2151_bus_cyc = ymsoc_bus_out_cyc;
assign ymsoc_wb2151_bus_stb = ymsoc_bus_out_stb;
assign ymsoc_bus_out_ack = ymsoc_wb2151_bus_ack;
assign ymsoc_wb2151_bus_we = ymsoc_bus_out_we;
assign ymsoc_wb2151_bus_cti = ymsoc_bus_out_cti;
assign ymsoc_wb2151_bus_bte = ymsoc_bus_out_bte;
assign ymsoc_bus_out_err = ymsoc_wb2151_bus_err;

// synthesis translate_off
reg dummy_d_2;
// synthesis translate_on
always @(*) begin
	ymsoc_time_up_clear <= 1'd0;
	if ((ymsoc_pending_re & ymsoc_pending_r[0])) begin
		ymsoc_time_up_clear <= 1'd1;
	end
// synthesis translate_off
	dummy_d_2 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_3;
// synthesis translate_on
always @(*) begin
	ymsoc_status_w <= 2'd0;
	ymsoc_status_w[0] <= ymsoc_time_up_status;
	ymsoc_status_w[1] <= ymsoc_sample_ready_status;
// synthesis translate_off
	dummy_d_3 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_4;
// synthesis translate_on
always @(*) begin
	ymsoc_sample_ready_clear <= 1'd0;
	if ((ymsoc_pending_re & ymsoc_pending_r[1])) begin
		ymsoc_sample_ready_clear <= 1'd1;
	end
// synthesis translate_off
	dummy_d_4 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_5;
// synthesis translate_on
always @(*) begin
	ymsoc_pending_w <= 2'd0;
	ymsoc_pending_w[0] <= ymsoc_time_up_pending;
	ymsoc_pending_w[1] <= ymsoc_sample_ready_pending;
// synthesis translate_off
	dummy_d_5 <= dummy_s;
// synthesis translate_on
end
assign ymsoc_irq = ((ymsoc_pending_w[0] & ymsoc_storage[0]) | (ymsoc_pending_w[1] & ymsoc_storage[1]));
assign ymsoc_time_up_status = ymsoc_time_up_trigger;
assign ymsoc_time_up_pending = ymsoc_time_up_trigger;
assign ymsoc_sample_ready_status = 1'd0;

// synthesis translate_off
reg dummy_d_6;
// synthesis translate_on
always @(*) begin
	ymsoc_reg_bus_dat_w <= 32'd0;
	ymsoc_rom_port_adr <= 16'd0;
	ymsoc_rom_port_wr <= 1'd0;
	ymsoc_rom_port_dat_w <= 32'd0;
	ymsoc_host_bus_dat_r <= 32'd0;
	ymsoc_reg_bus_adr <= 16'd0;
	ymsoc_reg_bus_wr <= 1'd0;
	case (ymsoc_host_bus_adr[17:16])
		1'd0: begin
			ymsoc_rom_port_dat_w <= ymsoc_host_bus_dat_w;
			ymsoc_host_bus_dat_r <= ymsoc_rom_port_dat_r;
			ymsoc_rom_port_adr <= ymsoc_host_bus_adr;
			ymsoc_rom_port_wr <= ymsoc_host_bus_wr;
		end
		2'd3: begin
			ymsoc_reg_bus_dat_w <= ymsoc_host_bus_dat_w;
			ymsoc_host_bus_dat_r <= ymsoc_reg_bus_dat_r;
			ymsoc_reg_bus_adr <= ymsoc_host_bus_adr;
			ymsoc_reg_bus_wr <= ymsoc_host_bus_wr;
		end
	endcase
// synthesis translate_off
	dummy_d_6 <= dummy_s;
// synthesis translate_on
end
assign ymsoc_cpu_reset = ymsoc_reg_ctl[0];

// synthesis translate_off
reg dummy_d_7;
// synthesis translate_on
always @(*) begin
	ymsoc_reg_bus_dat_r <= 32'd0;
	case (ymsoc_reg_bus_adr[1:0])
		1'd0: begin
			ymsoc_reg_bus_dat_r <= ymsoc_reg_ctl;
		end
		1'd1: begin
			ymsoc_reg_bus_dat_r <= ymsoc_reg_size;
		end
	endcase
// synthesis translate_off
	dummy_d_7 <= dummy_s;
// synthesis translate_on
end
assign audio_a0 = ymsoc_deltasigma0_out;
assign audio_a1 = ymsoc_deltasigma1_out;
assign ymsoc_deltasigma0_data = ymsoc_inp_dacleft;
assign ymsoc_deltasigma1_data = ymsoc_inp_dacright;
assign ymsoc_deltasigma0_delta = (ymsoc_deltasigma0_out <<< 5'd16);
assign ymsoc_deltasigma0_out = ymsoc_deltasigma0_sigma[16];
assign ymsoc_deltasigma1_delta = (ymsoc_deltasigma1_out <<< 5'd16);
assign ymsoc_deltasigma1_out = ymsoc_deltasigma1_sigma[16];
assign sys_clk = clk32;
assign arb_clk = clk32;
assign por_clk = clk32;
assign arb_rst = crg_int_rst;
assign sys_rst = (crg_int_rst | crg_manual_reset);
assign ym2151_clk = crg_ym_clk;
assign ym2151_rst = (crg_reset_cnt != 1'd0);
assign read = (~command[0]);
assign addr_space = command[2:1];
assign in_data = sin_in_data;
assign sout_out_data = out_data;
assign sin_take = rd;
assign sout_load = wr;
assign tx = sout_tx;
assign sin_rx = rx;
assign tx_empty = sout_empty;
assign rx_empty = sin_empty;
assign tx_ov = sout_overrun;
assign rx_ov = sin_overrun;
assign sout_shift = shift_out_strobe;
assign sin_shift = shift_in_strobe;
assign out_active = (~sout_empty);
assign in_active = sin_busy;

// synthesis translate_off
reg dummy_d_8;
// synthesis translate_on
always @(*) begin
	sout_tx <= 1'd0;
	if (sout_empty) begin
		sout_tx <= 1'd1;
	end else begin
		sout_tx <= sout_reg[0];
	end
// synthesis translate_off
	dummy_d_8 <= dummy_s;
// synthesis translate_on
end
assign sin_edge = ((sin_rx_prev == 1'd1) & (sin_sync_rx == 1'd0));

// synthesis translate_off
reg dummy_d_9;
// synthesis translate_on
always @(*) begin
	f_next_value0 <= 8'd0;
	f_next_value_ce0 <= 1'd0;
	out_data <= 8'd0;
	t_next_value1 <= 8'd0;
	t_next_value_ce1 <= 1'd0;
	wr <= 1'd0;
	rd <= 1'd0;
	data_word_next_value2 <= 2'd0;
	data_word_next_value_ce2 <= 1'd0;
	bus_dat_w <= 32'd0;
	bus_adr <= 18'd0;
	bus_wr <= 1'd0;
	f_next_value1 <= 8'd0;
	f_next_value_ce1 <= 1'd0;
	f_t_next_value <= 8'd0;
	f_t_next_value_ce <= 1'd0;
	f_f_next_value <= 8'd0;
	f_f_next_value_ce <= 1'd0;
	next_state <= 3'd0;
	command_next_value0 <= 8'd0;
	command_next_value_ce0 <= 1'd0;
	t_next_value0 <= 8'd0;
	t_next_value_ce0 <= 1'd0;
	addr_word_next_value1 <= 1'd0;
	addr_word_next_value_ce1 <= 1'd0;
	next_state <= state;
	case (state)
		1'd1: begin
			if ((~rx_empty)) begin
				rd <= 1'd1;
				if ((addr_word == 1'd1)) begin
					t_next_value0 <= in_data;
					t_next_value_ce0 <= 1'd1;
					addr_word_next_value1 <= 1'd0;
					addr_word_next_value_ce1 <= 1'd1;
					if (read) begin
						bus_wr <= 1'd0;
						bus_adr <= {addr_space, addr};
						next_state <= 3'd4;
					end else begin
						next_state <= 2'd2;
					end
				end else begin
					f_next_value0 <= in_data;
					f_next_value_ce0 <= 1'd1;
					addr_word_next_value1 <= (addr_word + 1'd1);
					addr_word_next_value_ce1 <= 1'd1;
				end
			end
		end
		2'd2: begin
			if ((~rx_empty)) begin
				rd <= 1'd1;
				if ((data_word == 2'd3)) begin
					t_next_value1 <= in_data;
					t_next_value_ce1 <= 1'd1;
					data_word_next_value2 <= 1'd0;
					data_word_next_value_ce2 <= 1'd1;
					next_state <= 2'd3;
				end else begin
					if ((data_word == 2'd2)) begin
						f_next_value1 <= in_data;
						f_next_value_ce1 <= 1'd1;
						data_word_next_value2 <= (data_word + 1'd1);
						data_word_next_value_ce2 <= 1'd1;
					end else begin
						if ((data_word == 1'd1)) begin
							f_t_next_value <= in_data;
							f_t_next_value_ce <= 1'd1;
							data_word_next_value2 <= (data_word + 1'd1);
							data_word_next_value_ce2 <= 1'd1;
						end else begin
							f_f_next_value <= in_data;
							f_f_next_value_ce <= 1'd1;
							data_word_next_value2 <= (data_word + 1'd1);
							data_word_next_value_ce2 <= 1'd1;
						end
					end
				end
			end
		end
		2'd3: begin
			bus_wr <= 1'd1;
			bus_adr <= {addr_space, addr};
			bus_dat_w <= data;
			next_state <= 1'd0;
		end
		3'd4: begin
			bus_wr <= 1'd0;
			bus_adr <= {addr_space, addr};
			if (tx_empty) begin
				wr <= 1'd1;
				if ((data_word == 2'd3)) begin
					out_data <= bus_dat_r[31:24];
					data_word_next_value2 <= 1'd0;
					data_word_next_value_ce2 <= 1'd1;
					next_state <= 1'd0;
				end else begin
					if ((data_word == 2'd2)) begin
						out_data <= bus_dat_r[23:16];
						data_word_next_value2 <= (data_word + 1'd1);
						data_word_next_value_ce2 <= 1'd1;
					end else begin
						if ((data_word == 1'd1)) begin
							out_data <= bus_dat_r[15:8];
							data_word_next_value2 <= (data_word + 1'd1);
							data_word_next_value_ce2 <= 1'd1;
						end else begin
							out_data <= bus_dat_r[7:0];
							data_word_next_value2 <= (data_word + 1'd1);
							data_word_next_value_ce2 <= 1'd1;
						end
					end
				end
			end
		end
		default: begin
			if ((~rx_empty)) begin
				next_state <= 1'd1;
				command_next_value0 <= in_data;
				command_next_value_ce0 <= 1'd1;
				rd <= 1'd1;
			end
		end
	endcase
// synthesis translate_off
	dummy_d_9 <= dummy_s;
// synthesis translate_on
end
assign shared_adr = array_muxed0;
assign shared_dat_w = array_muxed1;
assign shared_sel = array_muxed2;
assign shared_cyc = array_muxed3;
assign shared_stb = array_muxed4;
assign shared_we = array_muxed5;
assign shared_cti = array_muxed6;
assign shared_bte = array_muxed7;
assign ymsoc_ibus_dat_r = shared_dat_r;
assign ymsoc_tmpu_dat_r = shared_dat_r;
assign ymsoc_ibus_ack = (shared_ack & (grant == 1'd0));
assign ymsoc_tmpu_ack = (shared_ack & (grant == 1'd1));
assign ymsoc_ibus_err = (shared_err & (grant == 1'd0));
assign ymsoc_tmpu_err = (shared_err & (grant == 1'd1));
assign request = {ymsoc_tmpu_cyc, ymsoc_ibus_cyc};

// synthesis translate_off
reg dummy_d_10;
// synthesis translate_on
always @(*) begin
	slave_sel <= 4'd0;
	slave_sel[0] <= (shared_adr[28:26] == 1'd0);
	slave_sel[1] <= (shared_adr[28:26] == 1'd1);
	slave_sel[2] <= (shared_adr[28:26] == 3'd6);
	slave_sel[3] <= (shared_adr[28:26] == 2'd3);
// synthesis translate_off
	dummy_d_10 <= dummy_s;
// synthesis translate_on
end
assign ymsoc_rom_bus_adr = shared_adr;
assign ymsoc_rom_bus_dat_w = shared_dat_w;
assign ymsoc_rom_bus_sel = shared_sel;
assign ymsoc_rom_bus_stb = shared_stb;
assign ymsoc_rom_bus_we = shared_we;
assign ymsoc_rom_bus_cti = shared_cti;
assign ymsoc_rom_bus_bte = shared_bte;
assign ymsoc_sram_bus_adr = shared_adr;
assign ymsoc_sram_bus_dat_w = shared_dat_w;
assign ymsoc_sram_bus_sel = shared_sel;
assign ymsoc_sram_bus_stb = shared_stb;
assign ymsoc_sram_bus_we = shared_we;
assign ymsoc_sram_bus_cti = shared_cti;
assign ymsoc_sram_bus_bte = shared_bte;
assign ymsoc_bus_wishbone_adr = shared_adr;
assign ymsoc_bus_wishbone_dat_w = shared_dat_w;
assign ymsoc_bus_wishbone_sel = shared_sel;
assign ymsoc_bus_wishbone_stb = shared_stb;
assign ymsoc_bus_wishbone_we = shared_we;
assign ymsoc_bus_wishbone_cti = shared_cti;
assign ymsoc_bus_wishbone_bte = shared_bte;
assign ymsoc_bus_bus_adr = shared_adr;
assign ymsoc_bus_bus_dat_w = shared_dat_w;
assign ymsoc_bus_bus_sel = shared_sel;
assign ymsoc_bus_bus_stb = shared_stb;
assign ymsoc_bus_bus_we = shared_we;
assign ymsoc_bus_bus_cti = shared_cti;
assign ymsoc_bus_bus_bte = shared_bte;
assign ymsoc_rom_bus_cyc = (shared_cyc & slave_sel[0]);
assign ymsoc_sram_bus_cyc = (shared_cyc & slave_sel[1]);
assign ymsoc_bus_wishbone_cyc = (shared_cyc & slave_sel[2]);
assign ymsoc_bus_bus_cyc = (shared_cyc & slave_sel[3]);
assign shared_ack = (((ymsoc_rom_bus_ack | ymsoc_sram_bus_ack) | ymsoc_bus_wishbone_ack) | ymsoc_bus_bus_ack);
assign shared_err = (((ymsoc_rom_bus_err | ymsoc_sram_bus_err) | ymsoc_bus_wishbone_err) | ymsoc_bus_bus_err);
assign shared_dat_r = (((({32{slave_sel_r[0]}} & ymsoc_rom_bus_dat_r) | ({32{slave_sel_r[1]}} & ymsoc_sram_bus_dat_r)) | ({32{slave_sel_r[2]}} & ymsoc_bus_wishbone_dat_r)) | ({32{slave_sel_r[3]}} & ymsoc_bus_bus_dat_r));
assign csrbank0_sel = (interface0_adr[13:9] == 3'd4);
assign csrbank0_enable_null0_r = interface0_dat_w[0];
assign csrbank0_enable_null0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[2:0] == 1'd0));
assign csrbank0_enable_prog0_r = interface0_dat_w[0];
assign csrbank0_enable_prog0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[2:0] == 1'd1));
assign csrbank0_prog_address3_r = interface0_dat_w[5:0];
assign csrbank0_prog_address3_re = ((csrbank0_sel & interface0_we) & (interface0_adr[2:0] == 2'd2));
assign csrbank0_prog_address2_r = interface0_dat_w[7:0];
assign csrbank0_prog_address2_re = ((csrbank0_sel & interface0_we) & (interface0_adr[2:0] == 2'd3));
assign csrbank0_prog_address1_r = interface0_dat_w[7:0];
assign csrbank0_prog_address1_re = ((csrbank0_sel & interface0_we) & (interface0_adr[2:0] == 3'd4));
assign csrbank0_prog_address0_r = interface0_dat_w[7:0];
assign csrbank0_prog_address0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[2:0] == 3'd5));
assign ymsoc_tmpu_enable_null_storage = ymsoc_tmpu_enable_null_storage_full;
assign csrbank0_enable_null0_w = ymsoc_tmpu_enable_null_storage_full;
assign ymsoc_tmpu_enable_prog_storage = ymsoc_tmpu_enable_prog_storage_full;
assign csrbank0_enable_prog0_w = ymsoc_tmpu_enable_prog_storage_full;
assign ymsoc_tmpu_prog_address_storage = ymsoc_tmpu_prog_address_storage_full[29:12];
assign csrbank0_prog_address3_w = ymsoc_tmpu_prog_address_storage_full[29:24];
assign csrbank0_prog_address2_w = ymsoc_tmpu_prog_address_storage_full[23:16];
assign csrbank0_prog_address1_w = {ymsoc_tmpu_prog_address_storage_full[15:12], {4{1'd0}}};
assign csrbank0_prog_address0_w = 1'd0;
assign csrbank1_sel = (interface1_adr[13:9] == 3'd5);
assign ymsoc_status_r = interface1_dat_w[1:0];
assign ymsoc_status_re = ((csrbank1_sel & interface1_we) & (interface1_adr[1:0] == 1'd0));
assign ymsoc_pending_r = interface1_dat_w[1:0];
assign ymsoc_pending_re = ((csrbank1_sel & interface1_we) & (interface1_adr[1:0] == 1'd1));
assign csrbank1_ev_enable0_r = interface1_dat_w[1:0];
assign csrbank1_ev_enable0_re = ((csrbank1_sel & interface1_we) & (interface1_adr[1:0] == 2'd2));
assign ymsoc_storage = ymsoc_storage_full[1:0];
assign csrbank1_ev_enable0_w = ymsoc_storage_full[1:0];
assign interface0_adr = ymsoc_interface_adr;
assign interface1_adr = ymsoc_interface_adr;
assign interface0_we = ymsoc_interface_we;
assign interface1_we = ymsoc_interface_we;
assign interface0_dat_w = ymsoc_interface_dat_w;
assign interface1_dat_w = ymsoc_interface_dat_w;
assign ymsoc_interface_dat_r = (interface0_dat_r | interface1_dat_r);

// synthesis translate_off
reg dummy_d_11;
// synthesis translate_on
always @(*) begin
	array_muxed0 <= 30'd0;
	case (grant)
		1'd0: begin
			array_muxed0 <= ymsoc_ibus_adr;
		end
		default: begin
			array_muxed0 <= ymsoc_tmpu_adr;
		end
	endcase
// synthesis translate_off
	dummy_d_11 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_12;
// synthesis translate_on
always @(*) begin
	array_muxed1 <= 32'd0;
	case (grant)
		1'd0: begin
			array_muxed1 <= ymsoc_ibus_dat_w;
		end
		default: begin
			array_muxed1 <= ymsoc_tmpu_dat_w;
		end
	endcase
// synthesis translate_off
	dummy_d_12 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_13;
// synthesis translate_on
always @(*) begin
	array_muxed2 <= 4'd0;
	case (grant)
		1'd0: begin
			array_muxed2 <= ymsoc_ibus_sel;
		end
		default: begin
			array_muxed2 <= ymsoc_tmpu_sel;
		end
	endcase
// synthesis translate_off
	dummy_d_13 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_14;
// synthesis translate_on
always @(*) begin
	array_muxed3 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed3 <= ymsoc_ibus_cyc;
		end
		default: begin
			array_muxed3 <= ymsoc_tmpu_cyc;
		end
	endcase
// synthesis translate_off
	dummy_d_14 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_15;
// synthesis translate_on
always @(*) begin
	array_muxed4 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed4 <= ymsoc_ibus_stb;
		end
		default: begin
			array_muxed4 <= ymsoc_tmpu_stb;
		end
	endcase
// synthesis translate_off
	dummy_d_15 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_16;
// synthesis translate_on
always @(*) begin
	array_muxed5 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed5 <= ymsoc_ibus_we;
		end
		default: begin
			array_muxed5 <= ymsoc_tmpu_we;
		end
	endcase
// synthesis translate_off
	dummy_d_16 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_17;
// synthesis translate_on
always @(*) begin
	array_muxed6 <= 3'd0;
	case (grant)
		1'd0: begin
			array_muxed6 <= ymsoc_ibus_cti;
		end
		default: begin
			array_muxed6 <= ymsoc_tmpu_cti;
		end
	endcase
// synthesis translate_off
	dummy_d_17 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_18;
// synthesis translate_on
always @(*) begin
	array_muxed7 <= 2'd0;
	case (grant)
		1'd0: begin
			array_muxed7 <= ymsoc_ibus_bte;
		end
		default: begin
			array_muxed7 <= ymsoc_tmpu_bte;
		end
	endcase
// synthesis translate_off
	dummy_d_18 <= dummy_s;
// synthesis translate_on
end
assign ymsoc_irq_n = xilinxmultiregimpl0_regs1;
assign ymsoc_sample = xilinxmultiregimpl1_regs1;

always @(posedge arb_clk) begin
	if (arb_rst) begin
		ymsoc_reg_ctl <= 32'd1;
		ymsoc_reg_size <= 16'd0;
		sout_empty <= 1'd1;
		sout_overrun <= 1'd0;
		sout_count <= 4'd0;
		sout_reg <= 10'd0;
		sin_in_data <= 8'd0;
		sin_empty <= 1'd1;
		sin_busy <= 1'd0;
		sin_overrun <= 1'd0;
		sin_sync_rx <= 1'd0;
		sin_reg <= 9'd0;
		sin_rx_prev <= 1'd0;
		sin_count <= 4'd0;
		shift_out_strobe <= 1'd0;
		shift_in_strobe <= 1'd0;
		in_counter <= 9'd0;
		out_counter <= 9'd0;
		command <= 8'd0;
		addr <= 16'd0;
		data <= 32'd0;
		addr_word <= 1'd0;
		data_word <= 2'd0;
		state <= 3'd0;
	end else begin
		if (ymsoc_reg_bus_wr) begin
			if ((ymsoc_reg_bus_adr[1:0] == 1'd0)) begin
				ymsoc_reg_ctl <= ymsoc_reg_bus_dat_w;
			end else begin
				if ((ymsoc_reg_bus_adr[1:0] == 1'd1)) begin
					ymsoc_reg_size <= ymsoc_reg_bus_dat_w;
				end
			end
		end
		if (sout_load) begin
			if (sout_empty) begin
				sout_reg[0] <= 1'd0;
				sout_reg[8:1] <= sout_out_data;
				sout_reg[9] <= 1'd1;
				sout_empty <= 1'd0;
				sout_overrun <= 1'd0;
				sout_count <= 1'd0;
			end else begin
				sout_overrun <= 1'd1;
			end
		end
		if (((~sout_empty) & sout_shift)) begin
			sout_reg[8:0] <= sout_reg[9:1];
			sout_reg[9] <= 1'd0;
			if ((sout_count == 4'd9)) begin
				sout_empty <= 1'd1;
				sout_count <= 1'd0;
			end else begin
				sout_count <= (sout_count + 1'd1);
			end
		end
		sin_sync_rx <= sin_rx;
		sin_rx_prev <= sin_sync_rx;
		if (sin_take) begin
			sin_empty <= 1'd1;
			sin_overrun <= 1'd0;
		end
		if (((~sin_busy) & sin_edge)) begin
			sin_busy <= 1'd1;
		end
		if ((sin_shift & sin_busy)) begin
			sin_reg[8] <= sin_sync_rx;
			sin_reg[7:0] <= sin_reg[8:1];
			if ((sin_count == 4'd9)) begin
				sin_in_data <= sin_reg[8:1];
				sin_count <= 1'd0;
				sin_busy <= 1'd0;
				if ((~sin_empty)) begin
					sin_overrun <= 1'd1;
				end else begin
					sin_empty <= 1'd0;
				end
			end else begin
				sin_count <= (sin_count + 1'd1);
			end
		end
		out_counter <= 1'd0;
		in_counter <= 1'd0;
		if (in_active) begin
			shift_in_strobe <= 1'd0;
			in_counter <= (in_counter + 1'd1);
			if ((in_counter == 8'd135)) begin
				shift_in_strobe <= 1'd1;
			end
			if ((in_counter == 9'd271)) begin
				in_counter <= 1'd0;
			end
		end
		if (out_active) begin
			shift_out_strobe <= 1'd0;
			out_counter <= (out_counter + 1'd1);
			if ((out_counter == 9'd271)) begin
				out_counter <= 1'd0;
				shift_out_strobe <= 1'd1;
			end
		end
		state <= next_state;
		if (command_next_value_ce0) begin
			command <= command_next_value0;
		end
		if (t_next_value_ce0) begin
			addr[15:8] <= t_next_value0;
		end
		if (addr_word_next_value_ce1) begin
			addr_word <= addr_word_next_value1;
		end
		if (f_next_value_ce0) begin
			addr[7:0] <= f_next_value0;
		end
		if (t_next_value_ce1) begin
			data[31:24] <= t_next_value1;
		end
		if (data_word_next_value_ce2) begin
			data_word <= data_word_next_value2;
		end
		if (f_next_value_ce1) begin
			data[23:16] <= f_next_value1;
		end
		if (f_t_next_value_ce) begin
			data[15:8] <= f_t_next_value;
		end
		if (f_f_next_value_ce) begin
			data[7:0] <= f_f_next_value;
		end
	end
end

always @(posedge por_clk) begin
	crg_int_rst <= 1'd0;
end

always @(posedge sys_clk) begin
	if (sys_rst) begin
		ymsoc_tmpu_enable_null_storage_full <= 1'd0;
		ymsoc_tmpu_enable_null_re <= 1'd0;
		ymsoc_tmpu_enable_prog_storage_full <= 1'd0;
		ymsoc_tmpu_enable_prog_re <= 1'd0;
		ymsoc_tmpu_prog_address_storage_full <= 30'd0;
		ymsoc_tmpu_prog_address_re <= 1'd0;
		ymsoc_tmpu_error <= 1'd0;
		ymsoc_rom_bus_ack <= 1'd0;
		ymsoc_sram_bus_ack <= 1'd0;
		ymsoc_interface_adr <= 14'd0;
		ymsoc_interface_we <= 1'd0;
		ymsoc_interface_dat_w <= 8'd0;
		ymsoc_bus_wishbone_dat_r <= 32'd0;
		ymsoc_bus_wishbone_ack <= 1'd0;
		ymsoc_counter <= 2'd0;
		ymsoc_mcyc_prev <= 1'd0;
		ymsoc_cyc_wait_count <= 4'd0;
		ymsoc_mstb_prev <= 1'd0;
		ymsoc_stb_wait_count <= 4'd0;
		ymsoc_sample_ready_pending <= 1'd0;
		ymsoc_storage_full <= 2'd0;
		ymsoc_re <= 1'd0;
		ymsoc_deltasigma0_sigma <= 17'd0;
		ymsoc_deltasigma1_sigma <= 17'd0;
		crg_ym_clk <= 1'd0;
		crg_cnt <= 2'd0;
		crg_reset_cnt <= 4'd8;
		grant <= 1'd0;
		slave_sel_r <= 4'd0;
		interface0_dat_r <= 8'd0;
		interface1_dat_r <= 8'd0;
	end else begin
		ymsoc_tmpu_error <= 1'd0;
		if ((ymsoc_tmpu_enable_null_storage & (ymsoc_dbus_adr[29:10] == 1'd0))) begin
			ymsoc_tmpu_error <= 1'd1;
		end
		if ((ymsoc_tmpu_enable_prog_storage & (ymsoc_dbus_adr[29:10] == ymsoc_tmpu_prog_address_storage))) begin
			ymsoc_tmpu_error <= 1'd1;
		end
		ymsoc_rom_bus_ack <= 1'd0;
		if (((ymsoc_rom_bus_cyc & ymsoc_rom_bus_stb) & (~ymsoc_rom_bus_ack))) begin
			ymsoc_rom_bus_ack <= 1'd1;
		end
		ymsoc_sram_bus_ack <= 1'd0;
		if (((ymsoc_sram_bus_cyc & ymsoc_sram_bus_stb) & (~ymsoc_sram_bus_ack))) begin
			ymsoc_sram_bus_ack <= 1'd1;
		end
		ymsoc_interface_we <= 1'd0;
		ymsoc_interface_dat_w <= ymsoc_bus_wishbone_dat_w;
		ymsoc_interface_adr <= ymsoc_bus_wishbone_adr;
		ymsoc_bus_wishbone_dat_r <= ymsoc_interface_dat_r;
		if ((ymsoc_counter == 1'd1)) begin
			ymsoc_interface_we <= ymsoc_bus_wishbone_we;
		end
		if ((ymsoc_counter == 2'd2)) begin
			ymsoc_bus_wishbone_ack <= 1'd1;
		end
		if ((ymsoc_counter == 2'd3)) begin
			ymsoc_bus_wishbone_ack <= 1'd0;
		end
		if ((ymsoc_counter != 1'd0)) begin
			ymsoc_counter <= (ymsoc_counter + 1'd1);
		end else begin
			if ((ymsoc_bus_wishbone_cyc & ymsoc_bus_wishbone_stb)) begin
				ymsoc_counter <= 1'd1;
			end
		end
		ymsoc_mcyc_prev <= ymsoc_bus_in_cyc;
		ymsoc_mstb_prev <= ymsoc_bus_in_stb;
		if ((ymsoc_cyc_wait_count != 1'd0)) begin
			ymsoc_cyc_wait_count <= (ymsoc_cyc_wait_count - 1'd1);
		end
		if ((ymsoc_stb_wait_count != 1'd0)) begin
			ymsoc_stb_wait_count <= (ymsoc_stb_wait_count - 1'd1);
		end
		if (ymsoc_mcyc_negedge) begin
			ymsoc_cyc_wait_count <= 4'd8;
		end
		if (ymsoc_mstb_negedge) begin
			ymsoc_stb_wait_count <= 4'd8;
		end
		if (ymsoc_sample_ready_clear) begin
			ymsoc_sample_ready_pending <= 1'd0;
		end
		if (ymsoc_sample_ready_trigger) begin
			ymsoc_sample_ready_pending <= 1'd1;
		end
		ymsoc_deltasigma0_sigma <= ((ymsoc_deltasigma0_data - ymsoc_deltasigma0_delta) + ymsoc_deltasigma0_sigma);
		ymsoc_deltasigma1_sigma <= ((ymsoc_deltasigma1_data - ymsoc_deltasigma1_delta) + ymsoc_deltasigma1_sigma);
		if ((crg_cnt == 2'd3)) begin
			crg_cnt <= 1'd0;
			crg_ym_clk <= (~crg_ym_clk);
		end else begin
			crg_cnt <= (crg_cnt + 1'd1);
		end
		if ((crg_reset_cnt != 1'd0)) begin
			crg_reset_cnt <= (crg_reset_cnt - 1'd1);
		end
		case (grant)
			1'd0: begin
				if ((~request[0])) begin
					if (request[1]) begin
						grant <= 1'd1;
					end
				end
			end
			1'd1: begin
				if ((~request[1])) begin
					if (request[0]) begin
						grant <= 1'd0;
					end
				end
			end
		endcase
		slave_sel_r <= slave_sel;
		interface0_dat_r <= 1'd0;
		if (csrbank0_sel) begin
			case (interface0_adr[2:0])
				1'd0: begin
					interface0_dat_r <= csrbank0_enable_null0_w;
				end
				1'd1: begin
					interface0_dat_r <= csrbank0_enable_prog0_w;
				end
				2'd2: begin
					interface0_dat_r <= csrbank0_prog_address3_w;
				end
				2'd3: begin
					interface0_dat_r <= csrbank0_prog_address2_w;
				end
				3'd4: begin
					interface0_dat_r <= csrbank0_prog_address1_w;
				end
				3'd5: begin
					interface0_dat_r <= csrbank0_prog_address0_w;
				end
			endcase
		end
		if (csrbank0_enable_null0_re) begin
			ymsoc_tmpu_enable_null_storage_full <= csrbank0_enable_null0_r;
		end
		ymsoc_tmpu_enable_null_re <= csrbank0_enable_null0_re;
		if (csrbank0_enable_prog0_re) begin
			ymsoc_tmpu_enable_prog_storage_full <= csrbank0_enable_prog0_r;
		end
		ymsoc_tmpu_enable_prog_re <= csrbank0_enable_prog0_re;
		if (csrbank0_prog_address3_re) begin
			ymsoc_tmpu_prog_address_storage_full[29:24] <= csrbank0_prog_address3_r;
		end
		if (csrbank0_prog_address2_re) begin
			ymsoc_tmpu_prog_address_storage_full[23:16] <= csrbank0_prog_address2_r;
		end
		if (csrbank0_prog_address1_re) begin
			ymsoc_tmpu_prog_address_storage_full[15:8] <= csrbank0_prog_address1_r;
		end
		if (csrbank0_prog_address0_re) begin
			ymsoc_tmpu_prog_address_storage_full[7:0] <= csrbank0_prog_address0_r;
		end
		ymsoc_tmpu_prog_address_re <= csrbank0_prog_address0_re;
		interface1_dat_r <= 1'd0;
		if (csrbank1_sel) begin
			case (interface1_adr[1:0])
				1'd0: begin
					interface1_dat_r <= ymsoc_status_w;
				end
				1'd1: begin
					interface1_dat_r <= ymsoc_pending_w;
				end
				2'd2: begin
					interface1_dat_r <= csrbank1_ev_enable0_w;
				end
			endcase
		end
		if (csrbank1_ev_enable0_re) begin
			ymsoc_storage_full[1:0] <= csrbank1_ev_enable0_r;
		end
		ymsoc_re <= csrbank1_ev_enable0_re;
	end
	xilinxmultiregimpl0_regs0 <= ymsoc_wb2151_bus_irq_n;
	xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0;
	xilinxmultiregimpl1_regs0 <= ymsoc_wb2151_out_sample;
	xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0;
end

always @(posedge ym2151_clk) begin
	if (ym2151_rst) begin
		ymsoc_wb2151_bus_ack <= 1'd0;
	end else begin
		ymsoc_wb2151_bus_ack <= 1'd0;
		if (((ymsoc_wb2151_bus_stb & ymsoc_wb2151_bus_cyc) & (~ymsoc_wb2151_bus_ack))) begin
			ymsoc_wb2151_bus_ack <= 1'd1;
		end
	end
end

lm32_cpu #(
	.eba_reset(32'h00000000)
) lm32_cpu (
	.D_ACK_I(ymsoc_dbus_ack),
	.D_DAT_I(ymsoc_dbus_dat_r),
	.D_ERR_I(ymsoc_dbus_err),
	.D_RTY_I(1'd0),
	.I_ACK_I(ymsoc_ibus_ack),
	.I_DAT_I(ymsoc_ibus_dat_r),
	.I_ERR_I(ymsoc_ibus_err),
	.I_RTY_I(1'd0),
	.clk_i(sys_clk),
	.interrupt(ymsoc_interrupt),
	.rst_i(sys_rst),
	.D_ADR_O(ymsoc_d_adr_o),
	.D_BTE_O(ymsoc_dbus_bte),
	.D_CTI_O(ymsoc_dbus_cti),
	.D_CYC_O(ymsoc_dbus_cyc),
	.D_DAT_O(ymsoc_dbus_dat_w),
	.D_SEL_O(ymsoc_dbus_sel),
	.D_STB_O(ymsoc_dbus_stb),
	.D_WE_O(ymsoc_dbus_we),
	.I_ADR_O(ymsoc_i_adr_o),
	.I_BTE_O(ymsoc_ibus_bte),
	.I_CTI_O(ymsoc_ibus_cti),
	.I_CYC_O(ymsoc_ibus_cyc),
	.I_DAT_O(ymsoc_ibus_dat_w),
	.I_SEL_O(ymsoc_ibus_sel),
	.I_STB_O(ymsoc_ibus_stb),
	.I_WE_O(ymsoc_ibus_we)
);

reg [31:0] mem[0:4095];
reg [11:0] memadr;
reg [11:0] memadr_1;
always @(posedge sys_clk) begin
	memadr <= ymsoc_rom_adr;
end

always @(posedge arb_clk) begin
	if (ymsoc_we)
		mem[ymsoc_adr] <= ymsoc_dat_w;
	memadr_1 <= ymsoc_adr;
end

assign ymsoc_rom_dat_r = mem[memadr];
assign ymsoc_dat_r = mem[memadr_1];

initial begin
	$readmemh("mem.init", mem);
end

reg [31:0] mem_1[0:1023];
reg [9:0] memadr_2;
always @(posedge sys_clk) begin
	if (ymsoc_sram_we[0])
		mem_1[ymsoc_sram_adr][7:0] <= ymsoc_sram_dat_w[7:0];
	if (ymsoc_sram_we[1])
		mem_1[ymsoc_sram_adr][15:8] <= ymsoc_sram_dat_w[15:8];
	if (ymsoc_sram_we[2])
		mem_1[ymsoc_sram_adr][23:16] <= ymsoc_sram_dat_w[23:16];
	if (ymsoc_sram_we[3])
		mem_1[ymsoc_sram_adr][31:24] <= ymsoc_sram_dat_w[31:24];
	memadr_2 <= ymsoc_sram_adr;
end

assign ymsoc_sram_dat_r = mem_1[memadr_2];

wb_async_reg wb_async_reg(
	.wbm_adr_i(ymsoc_bus_in_full),
	.wbm_clk(sys_clk),
	.wbm_cyc_i(ymsoc_cyc_qual),
	.wbm_dat_i(ymsoc_bus_in_dat_w),
	.wbm_rst(sys_rst),
	.wbm_sel_i(ymsoc_bus_in_sel),
	.wbm_stb_i(ymsoc_stb_qual),
	.wbm_we_i(ymsoc_bus_in_we),
	.wbs_ack_i(ymsoc_bus_out_ack),
	.wbs_clk(ym2151_clk),
	.wbs_dat_i(ymsoc_bus_out_dat_r),
	.wbs_err_i(ymsoc_bus_out_err),
	.wbs_rst(ym2151_rst),
	.wbm_ack_o(ymsoc_bus_in_ack),
	.wbm_dat_o(ymsoc_bus_in_dat_r),
	.wbm_err_o(ymsoc_bus_in_err),
	.wbs_adr_o(ymsoc_bus_out_full),
	.wbs_cyc_o(ymsoc_bus_out_cyc),
	.wbs_dat_o(ymsoc_bus_out_dat_w),
	.wbs_sel_o(ymsoc_bus_out_sel),
	.wbs_stb_o(ymsoc_bus_out_stb),
	.wbs_we_o(ymsoc_bus_out_we)
);

jt51 jt51(
	.a0(ymsoc_wb2151_bus_a0),
	.clk(ym2151_clk),
	.cs_n(ymsoc_wb2151_bus_cs_n),
	.d_in(ymsoc_wb2151_bus_d_in),
	.rst(ym2151_rst),
	.wr_n(ymsoc_wb2151_bus_wr_n),
	.ct1(ymsoc_wb2151_out_ct1),
	.ct2(ymsoc_wb2151_out_ct2),
	.d_out(ymsoc_wb2151_bus_d_out),
	.dacleft(ymsoc_wb2151_out_dacleft),
	.dacright(ymsoc_wb2151_out_dacright),
	.irq_n(ymsoc_wb2151_bus_irq_n),
	.p1(ymsoc_wb2151_out_p1),
	.sample(ymsoc_wb2151_out_sample)
);

endmodule