Xilinx Optimizes Out Sequential Logic

minispartan6.py

#!/usr/bin/env python3

import argparse
from fractions import Fraction

from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.build.platforms import minispartan6
from migen.build.generic_platform import *


from misoc.integration.soc_core import *
from misoc.integration.builder import *

from misoc.cores.gpio import GPIOOut


# class BaseSoC(SoCSDRAM):
class BaseSoC(SoCCore):
    csr_map.update(SoCCore.csr_map)

    def __init__(self, **kwargs):
        clk_freq = 32*1000000
        platform = minispartan6.Platform(device="xc6slx25")
        SoCCore.__init__(self, platform, clk_freq,
                  integrated_rom_size=0x8000, **kwargs)

        leds = Cat((platform.request("user_led") for p in range(8)))
        self.submodules.leds = GPIOOut(leds)

# Comment these three lines out; Xilinx will no longer optimize out logic.
        clk32 = platform.request("clk32")
        self.clock_domains.cd_sys = ClockDomain()
        self.clock_domains.cd_por = ClockDomain()
        pulse = Signal(reset=1)
        self.comb += [self.cd_por.clk.eq(clk32)]
        self.comb += [self.cd_sys.clk.eq(clk32)]
        self.comb += [self.cd_sys.rst.eq(pulse)]
        self.sync.por += [pulse.eq(0)]


def main():
    parser = argparse.ArgumentParser(description="MiSoC port to the MiniSpartan6")
    builder_args(parser)
    soc_core_args(parser)
    args = parser.parse_args()

    soc = BaseSoC(**soc_core_argdict(args))
    builder = Builder(soc, **builder_argdict(args))
    builder.build()


if __name__ == "__main__":
    main()

top.v

/* Machine-generated using Migen */
module top(
	output reg serial_tx,
	input serial_rx,
	output user_led,
	output user_led_1,
	output user_led_2,
	output user_led_3,
	output user_led_4,
	output user_led_5,
	output user_led_6,
	output user_led_7,
	input clk32
);

wire [29:0] ibus_adr;
wire [31:0] ibus_dat_w;
wire [31:0] ibus_dat_r;
wire [3:0] ibus_sel;
wire ibus_cyc;
wire ibus_stb;
wire ibus_ack;
wire ibus_we;
wire [2:0] ibus_cti;
wire [1:0] ibus_bte;
wire ibus_err;
wire [29:0] dbus_adr;
wire [31:0] dbus_dat_w;
wire [31:0] dbus_dat_r;
wire [3:0] dbus_sel;
wire dbus_cyc;
wire dbus_stb;
wire dbus_ack;
wire dbus_we;
wire [2:0] dbus_cti;
wire [1:0] dbus_bte;
wire dbus_err;
reg [31:0] interrupt = 1'd0;
wire [31:0] i_adr_o;
wire [31:0] d_adr_o;
wire [29:0] rom_bus_adr;
wire [31:0] rom_bus_dat_w;
wire [31:0] rom_bus_dat_r;
wire [3:0] rom_bus_sel;
wire rom_bus_cyc;
wire rom_bus_stb;
reg rom_bus_ack = 1'd0;
wire rom_bus_we;
wire [2:0] rom_bus_cti;
wire [1:0] rom_bus_bte;
reg rom_bus_err = 1'd0;
wire [12:0] rom_adr;
wire [31:0] rom_dat_r;
wire [29:0] sram_bus_adr;
wire [31:0] sram_bus_dat_w;
wire [31:0] sram_bus_dat_r;
wire [3:0] sram_bus_sel;
wire sram_bus_cyc;
wire sram_bus_stb;
reg sram_bus_ack = 1'd0;
wire sram_bus_we;
wire [2:0] sram_bus_cti;
wire [1:0] sram_bus_bte;
reg sram_bus_err = 1'd0;
wire [9:0] sram_adr;
wire [31:0] sram_dat_r;
reg [3:0] sram_we = 1'd0;
wire [31:0] sram_dat_w;
wire [29:0] main_ram_bus_adr;
wire [31:0] main_ram_bus_dat_w;
wire [31:0] main_ram_bus_dat_r;
wire [3:0] main_ram_bus_sel;
wire main_ram_bus_cyc;
wire main_ram_bus_stb;
reg main_ram_bus_ack = 1'd0;
wire main_ram_bus_we;
wire [2:0] main_ram_bus_cti;
wire [1:0] main_ram_bus_bte;
reg main_ram_bus_err = 1'd0;
wire [11:0] main_ram_adr;
wire [31:0] main_ram_dat_r;
reg [3:0] main_ram_we = 1'd0;
wire [31:0] main_ram_dat_w;
reg [13:0] interface_adr = 1'd0;
reg interface_we = 1'd0;
reg [7:0] interface_dat_w = 1'd0;
wire [7:0] interface_dat_r;
wire [29:0] bus_wishbone_adr;
wire [31:0] bus_wishbone_dat_w;
reg [31:0] bus_wishbone_dat_r = 1'd0;
wire [3:0] bus_wishbone_sel;
wire bus_wishbone_cyc;
wire bus_wishbone_stb;
reg bus_wishbone_ack = 1'd0;
wire bus_wishbone_we;
wire [2:0] bus_wishbone_cti;
wire [1:0] bus_wishbone_bte;
reg bus_wishbone_err = 1'd0;
reg [1:0] counter = 1'd0;
reg [31:0] uart_phy_storage_full = 24'd15461882;
wire [31:0] uart_phy_storage;
reg uart_phy_re = 1'd0;
wire uart_phy_sink_stb;
reg uart_phy_sink_ack = 1'd0;
wire uart_phy_sink_eop;
wire [7:0] uart_phy_sink_payload_data;
reg uart_phy_uart_clk_txen = 1'd0;
reg [31:0] uart_phy_phase_accumulator_tx = 1'd0;
reg [7:0] uart_phy_tx_reg = 1'd0;
reg [3:0] uart_phy_tx_bitcount = 1'd0;
reg uart_phy_tx_busy = 1'd0;
reg uart_phy_source_stb = 1'd0;
wire uart_phy_source_ack;
reg uart_phy_source_eop = 1'd0;
reg [7:0] uart_phy_source_payload_data = 1'd0;
reg uart_phy_uart_clk_rxen = 1'd0;
reg [31:0] uart_phy_phase_accumulator_rx = 1'd0;
wire uart_phy_rx;
reg uart_phy_rx_r = 1'd0;
reg [7:0] uart_phy_rx_reg = 1'd0;
reg [3:0] uart_phy_rx_bitcount = 1'd0;
reg uart_phy_rx_busy = 1'd0;
wire uart_rxtx_re;
wire [7:0] uart_rxtx_r;
wire [7:0] uart_rxtx_w;
wire uart_txfull_status;
wire uart_rxempty_status;
wire uart_irq;
wire uart_tx_status;
reg uart_tx_pending = 1'd0;
wire uart_tx_trigger;
reg uart_tx_clear = 1'd0;
reg uart_tx_old_trigger = 1'd0;
wire uart_rx_status;
reg uart_rx_pending = 1'd0;
wire uart_rx_trigger;
reg uart_rx_clear = 1'd0;
reg uart_rx_old_trigger = 1'd0;
wire uart_status_re;
wire [1:0] uart_status_r;
reg [1:0] uart_status_w = 1'd0;
wire uart_pending_re;
wire [1:0] uart_pending_r;
reg [1:0] uart_pending_w = 1'd0;
reg [1:0] uart_storage_full = 1'd0;
wire [1:0] uart_storage;
reg uart_re = 1'd0;
wire uart_tx_fifo_sink_stb;
wire uart_tx_fifo_sink_ack;
reg uart_tx_fifo_sink_eop = 1'd0;
wire [7:0] uart_tx_fifo_sink_payload_data;
wire uart_tx_fifo_source_stb;
wire uart_tx_fifo_source_ack;
wire uart_tx_fifo_source_eop;
wire [7:0] uart_tx_fifo_source_payload_data;
wire uart_tx_fifo_syncfifo_we;
wire uart_tx_fifo_syncfifo_writable;
wire uart_tx_fifo_syncfifo_re;
wire uart_tx_fifo_syncfifo_readable;
wire [8:0] uart_tx_fifo_syncfifo_din;
wire [8:0] uart_tx_fifo_syncfifo_dout;
reg [4:0] uart_tx_fifo_level = 1'd0;
reg uart_tx_fifo_replace = 1'd0;
reg [3:0] uart_tx_fifo_produce = 1'd0;
reg [3:0] uart_tx_fifo_consume = 1'd0;
reg [3:0] uart_tx_fifo_wrport_adr = 1'd0;
wire [8:0] uart_tx_fifo_wrport_dat_r;
wire uart_tx_fifo_wrport_we;
wire [8:0] uart_tx_fifo_wrport_dat_w;
wire uart_tx_fifo_do_read;
wire [3:0] uart_tx_fifo_rdport_adr;
wire [8:0] uart_tx_fifo_rdport_dat_r;
wire [7:0] uart_tx_fifo_fifo_in_payload_data;
wire uart_tx_fifo_fifo_in_eop;
wire [7:0] uart_tx_fifo_fifo_out_payload_data;
wire uart_tx_fifo_fifo_out_eop;
wire uart_rx_fifo_sink_stb;
wire uart_rx_fifo_sink_ack;
wire uart_rx_fifo_sink_eop;
wire [7:0] uart_rx_fifo_sink_payload_data;
wire uart_rx_fifo_source_stb;
wire uart_rx_fifo_source_ack;
wire uart_rx_fifo_source_eop;
wire [7:0] uart_rx_fifo_source_payload_data;
wire uart_rx_fifo_syncfifo_we;
wire uart_rx_fifo_syncfifo_writable;
wire uart_rx_fifo_syncfifo_re;
wire uart_rx_fifo_syncfifo_readable;
wire [8:0] uart_rx_fifo_syncfifo_din;
wire [8:0] uart_rx_fifo_syncfifo_dout;
reg [4:0] uart_rx_fifo_level = 1'd0;
reg uart_rx_fifo_replace = 1'd0;
reg [3:0] uart_rx_fifo_produce = 1'd0;
reg [3:0] uart_rx_fifo_consume = 1'd0;
reg [3:0] uart_rx_fifo_wrport_adr = 1'd0;
wire [8:0] uart_rx_fifo_wrport_dat_r;
wire uart_rx_fifo_wrport_we;
wire [8:0] uart_rx_fifo_wrport_dat_w;
wire uart_rx_fifo_do_read;
wire [3:0] uart_rx_fifo_rdport_adr;
wire [8:0] uart_rx_fifo_rdport_dat_r;
wire [7:0] uart_rx_fifo_fifo_in_payload_data;
wire uart_rx_fifo_fifo_in_eop;
wire [7:0] uart_rx_fifo_fifo_out_payload_data;
wire uart_rx_fifo_fifo_out_eop;
reg [31:0] timer0_load_storage_full = 1'd0;
wire [31:0] timer0_load_storage;
reg timer0_load_re = 1'd0;
reg [31:0] timer0_reload_storage_full = 1'd0;
wire [31:0] timer0_reload_storage;
reg timer0_reload_re = 1'd0;
reg timer0_en_storage_full = 1'd0;
wire timer0_en_storage;
reg timer0_en_re = 1'd0;
wire timer0_update_value_re;
wire timer0_update_value_r;
reg timer0_update_value_w = 1'd0;
reg [31:0] timer0_value_status = 1'd0;
wire timer0_irq;
wire timer0_zero_status;
reg timer0_zero_pending = 1'd0;
wire timer0_zero_trigger;
reg timer0_zero_clear = 1'd0;
reg timer0_zero_old_trigger = 1'd0;
wire timer0_eventmanager_status_re;
wire timer0_eventmanager_status_r;
wire timer0_eventmanager_status_w;
wire timer0_eventmanager_pending_re;
wire timer0_eventmanager_pending_r;
wire timer0_eventmanager_pending_w;
reg timer0_eventmanager_storage_full = 1'd0;
wire timer0_eventmanager_storage;
reg timer0_eventmanager_re = 1'd0;
reg [31:0] timer0_value = 1'd0;
reg [7:0] leds_storage_full = 1'd0;
wire [7:0] leds_storage;
reg leds_re = 1'd0;
wire sys_clk;
reg sys_rst = 1'd0;
wire [29:0] shared_adr;
wire [31:0] shared_dat_w;
wire [31:0] shared_dat_r;
wire [3:0] shared_sel;
wire shared_cyc;
wire shared_stb;
wire shared_ack;
wire shared_we;
wire [2:0] shared_cti;
wire [1:0] shared_bte;
wire shared_err;
wire [1:0] request;
reg grant = 1'd0;
reg [3:0] slave_sel = 1'd0;
reg [3:0] slave_sel_r = 1'd0;
wire [13:0] interface0_adr;
wire interface0_we;
wire [7:0] interface0_dat_w;
reg [7:0] interface0_dat_r = 1'd0;
wire csrbank0_out0_re;
wire [7:0] csrbank0_out0_r;
wire [7:0] csrbank0_out0_w;
wire csrbank0_sel;
wire [13:0] interface1_adr;
wire interface1_we;
wire [7:0] interface1_dat_w;
reg [7:0] interface1_dat_r = 1'd0;
wire csrbank1_load3_re;
wire [7:0] csrbank1_load3_r;
wire [7:0] csrbank1_load3_w;
wire csrbank1_load2_re;
wire [7:0] csrbank1_load2_r;
wire [7:0] csrbank1_load2_w;
wire csrbank1_load1_re;
wire [7:0] csrbank1_load1_r;
wire [7:0] csrbank1_load1_w;
wire csrbank1_load0_re;
wire [7:0] csrbank1_load0_r;
wire [7:0] csrbank1_load0_w;
wire csrbank1_reload3_re;
wire [7:0] csrbank1_reload3_r;
wire [7:0] csrbank1_reload3_w;
wire csrbank1_reload2_re;
wire [7:0] csrbank1_reload2_r;
wire [7:0] csrbank1_reload2_w;
wire csrbank1_reload1_re;
wire [7:0] csrbank1_reload1_r;
wire [7:0] csrbank1_reload1_w;
wire csrbank1_reload0_re;
wire [7:0] csrbank1_reload0_r;
wire [7:0] csrbank1_reload0_w;
wire csrbank1_en0_re;
wire csrbank1_en0_r;
wire csrbank1_en0_w;
wire csrbank1_value3_re;
wire [7:0] csrbank1_value3_r;
wire [7:0] csrbank1_value3_w;
wire csrbank1_value2_re;
wire [7:0] csrbank1_value2_r;
wire [7:0] csrbank1_value2_w;
wire csrbank1_value1_re;
wire [7:0] csrbank1_value1_r;
wire [7:0] csrbank1_value1_w;
wire csrbank1_value0_re;
wire [7:0] csrbank1_value0_r;
wire [7:0] csrbank1_value0_w;
wire csrbank1_ev_enable0_re;
wire csrbank1_ev_enable0_r;
wire csrbank1_ev_enable0_w;
wire csrbank1_sel;
wire [13:0] interface2_adr;
wire interface2_we;
wire [7:0] interface2_dat_w;
reg [7:0] interface2_dat_r = 1'd0;
wire csrbank2_txfull_re;
wire csrbank2_txfull_r;
wire csrbank2_txfull_w;
wire csrbank2_rxempty_re;
wire csrbank2_rxempty_r;
wire csrbank2_rxempty_w;
wire csrbank2_ev_enable0_re;
wire [1:0] csrbank2_ev_enable0_r;
wire [1:0] csrbank2_ev_enable0_w;
wire csrbank2_sel;
wire [13:0] interface3_adr;
wire interface3_we;
wire [7:0] interface3_dat_w;
reg [7:0] interface3_dat_r = 1'd0;
wire csrbank3_tuning_word3_re;
wire [7:0] csrbank3_tuning_word3_r;
wire [7:0] csrbank3_tuning_word3_w;
wire csrbank3_tuning_word2_re;
wire [7:0] csrbank3_tuning_word2_r;
wire [7:0] csrbank3_tuning_word2_w;
wire csrbank3_tuning_word1_re;
wire [7:0] csrbank3_tuning_word1_r;
wire [7:0] csrbank3_tuning_word1_w;
wire csrbank3_tuning_word0_re;
wire [7:0] csrbank3_tuning_word0_r;
wire [7:0] csrbank3_tuning_word0_w;
wire csrbank3_sel;
reg [29:0] array_muxed0 = 1'd0;
reg [31:0] array_muxed1 = 1'd0;
reg [3:0] array_muxed2 = 1'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg [2:0] array_muxed6 = 1'd0;
reg [1:0] array_muxed7 = 1'd0;
reg regs0 = 1'd0;
reg regs1 = 1'd0;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign sys_clk = clk32;

// synthesis translate_off
reg dummy_d;
// synthesis translate_on
always @(*) begin
	interrupt <= 1'd0;
	interrupt[0] <= uart_irq;
	interrupt[1] <= timer0_irq;
// synthesis translate_off
	dummy_d <= dummy_s;
// synthesis translate_on
end
assign ibus_adr = i_adr_o[31:2];
assign dbus_adr = d_adr_o[31:2];
assign rom_adr = rom_bus_adr[12:0];
assign rom_bus_dat_r = rom_dat_r;

// synthesis translate_off
reg dummy_d_1;
// synthesis translate_on
always @(*) begin
	sram_we <= 1'd0;
	sram_we[0] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[0]);
	sram_we[1] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[1]);
	sram_we[2] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[2]);
	sram_we[3] <= (((sram_bus_cyc & sram_bus_stb) & sram_bus_we) & sram_bus_sel[3]);
// synthesis translate_off
	dummy_d_1 <= dummy_s;
// synthesis translate_on
end
assign sram_adr = sram_bus_adr[9:0];
assign sram_bus_dat_r = sram_dat_r;
assign sram_dat_w = sram_bus_dat_w;

// synthesis translate_off
reg dummy_d_2;
// synthesis translate_on
always @(*) begin
	main_ram_we <= 1'd0;
	main_ram_we[0] <= (((main_ram_bus_cyc & main_ram_bus_stb) & main_ram_bus_we) & main_ram_bus_sel[0]);
	main_ram_we[1] <= (((main_ram_bus_cyc & main_ram_bus_stb) & main_ram_bus_we) & main_ram_bus_sel[1]);
	main_ram_we[2] <= (((main_ram_bus_cyc & main_ram_bus_stb) & main_ram_bus_we) & main_ram_bus_sel[2]);
	main_ram_we[3] <= (((main_ram_bus_cyc & main_ram_bus_stb) & main_ram_bus_we) & main_ram_bus_sel[3]);
// synthesis translate_off
	dummy_d_2 <= dummy_s;
// synthesis translate_on
end
assign main_ram_adr = main_ram_bus_adr[11:0];
assign main_ram_bus_dat_r = main_ram_dat_r;
assign main_ram_dat_w = main_ram_bus_dat_w;
assign uart_tx_fifo_sink_stb = uart_rxtx_re;
assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
assign uart_txfull_status = (~uart_tx_fifo_sink_ack);
assign uart_phy_sink_stb = uart_tx_fifo_source_stb;
assign uart_tx_fifo_source_ack = uart_phy_sink_ack;
assign uart_phy_sink_eop = uart_tx_fifo_source_eop;
assign uart_phy_sink_payload_data = uart_tx_fifo_source_payload_data;
assign uart_tx_trigger = (~uart_tx_fifo_sink_ack);
assign uart_rx_fifo_sink_stb = uart_phy_source_stb;
assign uart_phy_source_ack = uart_rx_fifo_sink_ack;
assign uart_rx_fifo_sink_eop = uart_phy_source_eop;
assign uart_rx_fifo_sink_payload_data = uart_phy_source_payload_data;
assign uart_rxempty_status = (~uart_rx_fifo_source_stb);
assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
assign uart_rx_fifo_source_ack = uart_rx_clear;
assign uart_rx_trigger = (~uart_rx_fifo_source_stb);

// synthesis translate_off
reg dummy_d_3;
// synthesis translate_on
always @(*) begin
	uart_tx_clear <= 1'd0;
	if ((uart_pending_re & uart_pending_r[0])) begin
		uart_tx_clear <= 1'd1;
	end
// synthesis translate_off
	dummy_d_3 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_4;
// synthesis translate_on
always @(*) begin
	uart_status_w <= 1'd0;
	uart_status_w[0] <= uart_tx_status;
	uart_status_w[1] <= uart_rx_status;
// synthesis translate_off
	dummy_d_4 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_5;
// synthesis translate_on
always @(*) begin
	uart_rx_clear <= 1'd0;
	if ((uart_pending_re & uart_pending_r[1])) begin
		uart_rx_clear <= 1'd1;
	end
// synthesis translate_off
	dummy_d_5 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_6;
// synthesis translate_on
always @(*) begin
	uart_pending_w <= 1'd0;
	uart_pending_w[0] <= uart_tx_pending;
	uart_pending_w[1] <= uart_rx_pending;
// synthesis translate_off
	dummy_d_6 <= dummy_s;
// synthesis translate_on
end
assign uart_irq = ((uart_pending_w[0] & uart_storage[0]) | (uart_pending_w[1] & uart_storage[1]));
assign uart_tx_status = uart_tx_trigger;
assign uart_rx_status = uart_rx_trigger;
assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_eop, uart_tx_fifo_fifo_in_payload_data};
assign {uart_tx_fifo_fifo_out_eop, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign uart_tx_fifo_sink_ack = uart_tx_fifo_syncfifo_writable;
assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_stb;
assign uart_tx_fifo_fifo_in_eop = uart_tx_fifo_sink_eop;
assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
assign uart_tx_fifo_source_stb = uart_tx_fifo_syncfifo_readable;
assign uart_tx_fifo_source_eop = uart_tx_fifo_fifo_out_eop;
assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
assign uart_tx_fifo_syncfifo_re = uart_tx_fifo_source_ack;

// synthesis translate_off
reg dummy_d_7;
// synthesis translate_on
always @(*) begin
	uart_tx_fifo_wrport_adr <= 1'd0;
	if (uart_tx_fifo_replace) begin
		uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1);
	end else begin
		uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce;
	end
// synthesis translate_off
	dummy_d_7 <= dummy_s;
// synthesis translate_on
end
assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level != 5'd16);
assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level != 1'd0);
assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_eop, uart_rx_fifo_fifo_in_payload_data};
assign {uart_rx_fifo_fifo_out_eop, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign uart_rx_fifo_sink_ack = uart_rx_fifo_syncfifo_writable;
assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_stb;
assign uart_rx_fifo_fifo_in_eop = uart_rx_fifo_sink_eop;
assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
assign uart_rx_fifo_source_stb = uart_rx_fifo_syncfifo_readable;
assign uart_rx_fifo_source_eop = uart_rx_fifo_fifo_out_eop;
assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
assign uart_rx_fifo_syncfifo_re = uart_rx_fifo_source_ack;

// synthesis translate_off
reg dummy_d_8;
// synthesis translate_on
always @(*) begin
	uart_rx_fifo_wrport_adr <= 1'd0;
	if (uart_rx_fifo_replace) begin
		uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1);
	end else begin
		uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce;
	end
// synthesis translate_off
	dummy_d_8 <= dummy_s;
// synthesis translate_on
end
assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level != 5'd16);
assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level != 1'd0);
assign timer0_zero_trigger = (timer0_value != 1'd0);
assign timer0_eventmanager_status_w = timer0_zero_status;

// synthesis translate_off
reg dummy_d_9;
// synthesis translate_on
always @(*) begin
	timer0_zero_clear <= 1'd0;
	if ((timer0_eventmanager_pending_re & timer0_eventmanager_pending_r)) begin
		timer0_zero_clear <= 1'd1;
	end
// synthesis translate_off
	dummy_d_9 <= dummy_s;
// synthesis translate_on
end
assign timer0_eventmanager_pending_w = timer0_zero_pending;
assign timer0_irq = (timer0_eventmanager_pending_w & timer0_eventmanager_storage);
assign timer0_zero_status = timer0_zero_trigger;
assign {user_led_7, user_led_6, user_led_5, user_led_4, user_led_3, user_led_2, user_led_1, user_led} = leds_storage;
assign shared_adr = array_muxed0;
assign shared_dat_w = array_muxed1;
assign shared_sel = array_muxed2;
assign shared_cyc = array_muxed3;
assign shared_stb = array_muxed4;
assign shared_we = array_muxed5;
assign shared_cti = array_muxed6;
assign shared_bte = array_muxed7;
assign ibus_dat_r = shared_dat_r;
assign dbus_dat_r = shared_dat_r;
assign ibus_ack = (shared_ack & (grant == 1'd0));
assign dbus_ack = (shared_ack & (grant == 1'd1));
assign ibus_err = (shared_err & (grant == 1'd0));
assign dbus_err = (shared_err & (grant == 1'd1));
assign request = {dbus_cyc, ibus_cyc};

// synthesis translate_off
reg dummy_d_10;
// synthesis translate_on
always @(*) begin
	slave_sel <= 1'd0;
	slave_sel[0] <= (shared_adr[28:26] == 1'd0);
	slave_sel[1] <= (shared_adr[28:26] == 1'd1);
	slave_sel[2] <= (shared_adr[28:26] == 3'd4);
	slave_sel[3] <= (shared_adr[28:26] == 3'd6);
// synthesis translate_off
	dummy_d_10 <= dummy_s;
// synthesis translate_on
end
assign rom_bus_adr = shared_adr;
assign rom_bus_dat_w = shared_dat_w;
assign rom_bus_sel = shared_sel;
assign rom_bus_stb = shared_stb;
assign rom_bus_we = shared_we;
assign rom_bus_cti = shared_cti;
assign rom_bus_bte = shared_bte;
assign sram_bus_adr = shared_adr;
assign sram_bus_dat_w = shared_dat_w;
assign sram_bus_sel = shared_sel;
assign sram_bus_stb = shared_stb;
assign sram_bus_we = shared_we;
assign sram_bus_cti = shared_cti;
assign sram_bus_bte = shared_bte;
assign main_ram_bus_adr = shared_adr;
assign main_ram_bus_dat_w = shared_dat_w;
assign main_ram_bus_sel = shared_sel;
assign main_ram_bus_stb = shared_stb;
assign main_ram_bus_we = shared_we;
assign main_ram_bus_cti = shared_cti;
assign main_ram_bus_bte = shared_bte;
assign bus_wishbone_adr = shared_adr;
assign bus_wishbone_dat_w = shared_dat_w;
assign bus_wishbone_sel = shared_sel;
assign bus_wishbone_stb = shared_stb;
assign bus_wishbone_we = shared_we;
assign bus_wishbone_cti = shared_cti;
assign bus_wishbone_bte = shared_bte;
assign rom_bus_cyc = (shared_cyc & slave_sel[0]);
assign sram_bus_cyc = (shared_cyc & slave_sel[1]);
assign main_ram_bus_cyc = (shared_cyc & slave_sel[2]);
assign bus_wishbone_cyc = (shared_cyc & slave_sel[3]);
assign shared_ack = (((rom_bus_ack | sram_bus_ack) | main_ram_bus_ack) | bus_wishbone_ack);
assign shared_err = (((rom_bus_err | sram_bus_err) | main_ram_bus_err) | bus_wishbone_err);
assign shared_dat_r = (((({32{slave_sel_r[0]}} & rom_bus_dat_r) | ({32{slave_sel_r[1]}} & sram_bus_dat_r)) | ({32{slave_sel_r[2]}} & main_ram_bus_dat_r)) | ({32{slave_sel_r[3]}} & bus_wishbone_dat_r));
assign csrbank0_sel = (interface0_adr[13:9] == 3'd6);
assign csrbank0_out0_r = interface0_dat_w[7:0];
assign csrbank0_out0_re = ((csrbank0_sel & interface0_we) & (interface0_adr[0] == 1'd0));
assign leds_storage = leds_storage_full[7:0];
assign csrbank0_out0_w = leds_storage_full[7:0];
assign csrbank1_sel = (interface1_adr[13:9] == 3'd4);
assign csrbank1_load3_r = interface1_dat_w[7:0];
assign csrbank1_load3_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 1'd0));
assign csrbank1_load2_r = interface1_dat_w[7:0];
assign csrbank1_load2_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 1'd1));
assign csrbank1_load1_r = interface1_dat_w[7:0];
assign csrbank1_load1_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 2'd2));
assign csrbank1_load0_r = interface1_dat_w[7:0];
assign csrbank1_load0_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 2'd3));
assign csrbank1_reload3_r = interface1_dat_w[7:0];
assign csrbank1_reload3_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 3'd4));
assign csrbank1_reload2_r = interface1_dat_w[7:0];
assign csrbank1_reload2_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 3'd5));
assign csrbank1_reload1_r = interface1_dat_w[7:0];
assign csrbank1_reload1_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 3'd6));
assign csrbank1_reload0_r = interface1_dat_w[7:0];
assign csrbank1_reload0_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 3'd7));
assign csrbank1_en0_r = interface1_dat_w[0];
assign csrbank1_en0_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 4'd8));
assign timer0_update_value_r = interface1_dat_w[0];
assign timer0_update_value_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 4'd9));
assign csrbank1_value3_r = interface1_dat_w[7:0];
assign csrbank1_value3_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 4'd10));
assign csrbank1_value2_r = interface1_dat_w[7:0];
assign csrbank1_value2_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 4'd11));
assign csrbank1_value1_r = interface1_dat_w[7:0];
assign csrbank1_value1_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 4'd12));
assign csrbank1_value0_r = interface1_dat_w[7:0];
assign csrbank1_value0_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 4'd13));
assign timer0_eventmanager_status_r = interface1_dat_w[0];
assign timer0_eventmanager_status_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 4'd14));
assign timer0_eventmanager_pending_r = interface1_dat_w[0];
assign timer0_eventmanager_pending_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 4'd15));
assign csrbank1_ev_enable0_r = interface1_dat_w[0];
assign csrbank1_ev_enable0_re = ((csrbank1_sel & interface1_we) & (interface1_adr[4:0] == 5'd16));
assign timer0_load_storage = timer0_load_storage_full[31:0];
assign csrbank1_load3_w = timer0_load_storage_full[31:24];
assign csrbank1_load2_w = timer0_load_storage_full[23:16];
assign csrbank1_load1_w = timer0_load_storage_full[15:8];
assign csrbank1_load0_w = timer0_load_storage_full[7:0];
assign timer0_reload_storage = timer0_reload_storage_full[31:0];
assign csrbank1_reload3_w = timer0_reload_storage_full[31:24];
assign csrbank1_reload2_w = timer0_reload_storage_full[23:16];
assign csrbank1_reload1_w = timer0_reload_storage_full[15:8];
assign csrbank1_reload0_w = timer0_reload_storage_full[7:0];
assign timer0_en_storage = timer0_en_storage_full;
assign csrbank1_en0_w = timer0_en_storage_full;
assign csrbank1_value3_w = timer0_value_status[31:24];
assign csrbank1_value2_w = timer0_value_status[23:16];
assign csrbank1_value1_w = timer0_value_status[15:8];
assign csrbank1_value0_w = timer0_value_status[7:0];
assign timer0_eventmanager_storage = timer0_eventmanager_storage_full;
assign csrbank1_ev_enable0_w = timer0_eventmanager_storage_full;
assign csrbank2_sel = (interface2_adr[13:9] == 2'd2);
assign uart_rxtx_r = interface2_dat_w[7:0];
assign uart_rxtx_re = ((csrbank2_sel & interface2_we) & (interface2_adr[2:0] == 1'd0));
assign csrbank2_txfull_r = interface2_dat_w[0];
assign csrbank2_txfull_re = ((csrbank2_sel & interface2_we) & (interface2_adr[2:0] == 1'd1));
assign csrbank2_rxempty_r = interface2_dat_w[0];
assign csrbank2_rxempty_re = ((csrbank2_sel & interface2_we) & (interface2_adr[2:0] == 2'd2));
assign uart_status_r = interface2_dat_w[1:0];
assign uart_status_re = ((csrbank2_sel & interface2_we) & (interface2_adr[2:0] == 2'd3));
assign uart_pending_r = interface2_dat_w[1:0];
assign uart_pending_re = ((csrbank2_sel & interface2_we) & (interface2_adr[2:0] == 3'd4));
assign csrbank2_ev_enable0_r = interface2_dat_w[1:0];
assign csrbank2_ev_enable0_re = ((csrbank2_sel & interface2_we) & (interface2_adr[2:0] == 3'd5));
assign csrbank2_txfull_w = uart_txfull_status;
assign csrbank2_rxempty_w = uart_rxempty_status;
assign uart_storage = uart_storage_full[1:0];
assign csrbank2_ev_enable0_w = uart_storage_full[1:0];
assign csrbank3_sel = (interface3_adr[13:9] == 1'd1);
assign csrbank3_tuning_word3_r = interface3_dat_w[7:0];
assign csrbank3_tuning_word3_re = ((csrbank3_sel & interface3_we) & (interface3_adr[1:0] == 1'd0));
assign csrbank3_tuning_word2_r = interface3_dat_w[7:0];
assign csrbank3_tuning_word2_re = ((csrbank3_sel & interface3_we) & (interface3_adr[1:0] == 1'd1));
assign csrbank3_tuning_word1_r = interface3_dat_w[7:0];
assign csrbank3_tuning_word1_re = ((csrbank3_sel & interface3_we) & (interface3_adr[1:0] == 2'd2));
assign csrbank3_tuning_word0_r = interface3_dat_w[7:0];
assign csrbank3_tuning_word0_re = ((csrbank3_sel & interface3_we) & (interface3_adr[1:0] == 2'd3));
assign uart_phy_storage = uart_phy_storage_full[31:0];
assign csrbank3_tuning_word3_w = uart_phy_storage_full[31:24];
assign csrbank3_tuning_word2_w = uart_phy_storage_full[23:16];
assign csrbank3_tuning_word1_w = uart_phy_storage_full[15:8];
assign csrbank3_tuning_word0_w = uart_phy_storage_full[7:0];
assign interface0_adr = interface_adr;
assign interface1_adr = interface_adr;
assign interface2_adr = interface_adr;
assign interface3_adr = interface_adr;
assign interface0_we = interface_we;
assign interface1_we = interface_we;
assign interface2_we = interface_we;
assign interface3_we = interface_we;
assign interface0_dat_w = interface_dat_w;
assign interface1_dat_w = interface_dat_w;
assign interface2_dat_w = interface_dat_w;
assign interface3_dat_w = interface_dat_w;
assign interface_dat_r = (((interface0_dat_r | interface1_dat_r) | interface2_dat_r) | interface3_dat_r);

// synthesis translate_off
reg dummy_d_11;
// synthesis translate_on
always @(*) begin
	array_muxed0 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed0 <= ibus_adr;
		end
		default: begin
			array_muxed0 <= dbus_adr;
		end
	endcase
// synthesis translate_off
	dummy_d_11 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_12;
// synthesis translate_on
always @(*) begin
	array_muxed1 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed1 <= ibus_dat_w;
		end
		default: begin
			array_muxed1 <= dbus_dat_w;
		end
	endcase
// synthesis translate_off
	dummy_d_12 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_13;
// synthesis translate_on
always @(*) begin
	array_muxed2 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed2 <= ibus_sel;
		end
		default: begin
			array_muxed2 <= dbus_sel;
		end
	endcase
// synthesis translate_off
	dummy_d_13 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_14;
// synthesis translate_on
always @(*) begin
	array_muxed3 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed3 <= ibus_cyc;
		end
		default: begin
			array_muxed3 <= dbus_cyc;
		end
	endcase
// synthesis translate_off
	dummy_d_14 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_15;
// synthesis translate_on
always @(*) begin
	array_muxed4 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed4 <= ibus_stb;
		end
		default: begin
			array_muxed4 <= dbus_stb;
		end
	endcase
// synthesis translate_off
	dummy_d_15 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_16;
// synthesis translate_on
always @(*) begin
	array_muxed5 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed5 <= ibus_we;
		end
		default: begin
			array_muxed5 <= dbus_we;
		end
	endcase
// synthesis translate_off
	dummy_d_16 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_17;
// synthesis translate_on
always @(*) begin
	array_muxed6 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed6 <= ibus_cti;
		end
		default: begin
			array_muxed6 <= dbus_cti;
		end
	endcase
// synthesis translate_off
	dummy_d_17 <= dummy_s;
// synthesis translate_on
end

// synthesis translate_off
reg dummy_d_18;
// synthesis translate_on
always @(*) begin
	array_muxed7 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed7 <= ibus_bte;
		end
		default: begin
			array_muxed7 <= dbus_bte;
		end
	endcase
// synthesis translate_off
	dummy_d_18 <= dummy_s;
// synthesis translate_on
end
assign uart_phy_rx = regs1;

always @(posedge sys_clk) begin
	if (sys_rst) begin
		rom_bus_ack <= 1'd0;
		sram_bus_ack <= 1'd0;
		main_ram_bus_ack <= 1'd0;
		interface_adr <= 1'd0;
		interface_we <= 1'd0;
		interface_dat_w <= 1'd0;
		bus_wishbone_dat_r <= 1'd0;
		bus_wishbone_ack <= 1'd0;
		counter <= 1'd0;
		serial_tx <= 1'd1;
		uart_phy_storage_full <= 24'd15461882;
		uart_phy_re <= 1'd0;
		uart_phy_sink_ack <= 1'd0;
		uart_phy_uart_clk_txen <= 1'd0;
		uart_phy_phase_accumulator_tx <= 1'd0;
		uart_phy_tx_reg <= 1'd0;
		uart_phy_tx_bitcount <= 1'd0;
		uart_phy_tx_busy <= 1'd0;
		uart_phy_source_stb <= 1'd0;
		uart_phy_source_payload_data <= 1'd0;
		uart_phy_uart_clk_rxen <= 1'd0;
		uart_phy_phase_accumulator_rx <= 1'd0;
		uart_phy_rx_r <= 1'd0;
		uart_phy_rx_reg <= 1'd0;
		uart_phy_rx_bitcount <= 1'd0;
		uart_phy_rx_busy <= 1'd0;
		uart_tx_pending <= 1'd0;
		uart_tx_old_trigger <= 1'd0;
		uart_rx_pending <= 1'd0;
		uart_rx_old_trigger <= 1'd0;
		uart_storage_full <= 1'd0;
		uart_re <= 1'd0;
		uart_tx_fifo_level <= 1'd0;
		uart_tx_fifo_produce <= 1'd0;
		uart_tx_fifo_consume <= 1'd0;
		uart_rx_fifo_level <= 1'd0;
		uart_rx_fifo_produce <= 1'd0;
		uart_rx_fifo_consume <= 1'd0;
		timer0_load_storage_full <= 1'd0;
		timer0_load_re <= 1'd0;
		timer0_reload_storage_full <= 1'd0;
		timer0_reload_re <= 1'd0;
		timer0_en_storage_full <= 1'd0;
		timer0_en_re <= 1'd0;
		timer0_value_status <= 1'd0;
		timer0_zero_pending <= 1'd0;
		timer0_zero_old_trigger <= 1'd0;
		timer0_eventmanager_storage_full <= 1'd0;
		timer0_eventmanager_re <= 1'd0;
		timer0_value <= 1'd0;
		leds_storage_full <= 1'd0;
		leds_re <= 1'd0;
		grant <= 1'd0;
		slave_sel_r <= 1'd0;
		interface0_dat_r <= 1'd0;
		interface1_dat_r <= 1'd0;
		interface2_dat_r <= 1'd0;
		interface3_dat_r <= 1'd0;
	end else begin
		rom_bus_ack <= 1'd0;
		if (((rom_bus_cyc & rom_bus_stb) & (~rom_bus_ack))) begin
			rom_bus_ack <= 1'd1;
		end
		sram_bus_ack <= 1'd0;
		if (((sram_bus_cyc & sram_bus_stb) & (~sram_bus_ack))) begin
			sram_bus_ack <= 1'd1;
		end
		main_ram_bus_ack <= 1'd0;
		if (((main_ram_bus_cyc & main_ram_bus_stb) & (~main_ram_bus_ack))) begin
			main_ram_bus_ack <= 1'd1;
		end
		interface_we <= 1'd0;
		interface_dat_w <= bus_wishbone_dat_w;
		interface_adr <= bus_wishbone_adr;
		bus_wishbone_dat_r <= interface_dat_r;
		if ((counter == 1'd1)) begin
			interface_we <= bus_wishbone_we;
		end
		if ((counter == 2'd2)) begin
			bus_wishbone_ack <= 1'd1;
		end
		if ((counter == 2'd3)) begin
			bus_wishbone_ack <= 1'd0;
		end
		if ((counter != 1'd0)) begin
			counter <= (counter + 1'd1);
		end else begin
			if ((bus_wishbone_cyc & bus_wishbone_stb)) begin
				counter <= 1'd1;
			end
		end
		uart_phy_sink_ack <= 1'd0;
		if (((uart_phy_sink_stb & (~uart_phy_tx_busy)) & (~uart_phy_sink_ack))) begin
			uart_phy_tx_reg <= uart_phy_sink_payload_data;
			uart_phy_tx_bitcount <= 1'd0;
			uart_phy_tx_busy <= 1'd1;
			serial_tx <= 1'd0;
		end else begin
			if ((uart_phy_uart_clk_txen & uart_phy_tx_busy)) begin
				uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1);
				if ((uart_phy_tx_bitcount == 4'd8)) begin
					serial_tx <= 1'd1;
				end else begin
					if ((uart_phy_tx_bitcount == 4'd9)) begin
						serial_tx <= 1'd1;
						uart_phy_tx_busy <= 1'd0;
						uart_phy_sink_ack <= 1'd1;
					end else begin
						serial_tx <= uart_phy_tx_reg[0];
						uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]};
					end
				end
			end
		end
		if (uart_phy_tx_busy) begin
			{uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= (uart_phy_phase_accumulator_tx + uart_phy_storage);
		end else begin
			{uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= 1'd0;
		end
		uart_phy_source_stb <= 1'd0;
		uart_phy_rx_r <= uart_phy_rx;
		if ((~uart_phy_rx_busy)) begin
			if (((~uart_phy_rx) & uart_phy_rx_r)) begin
				uart_phy_rx_busy <= 1'd1;
				uart_phy_rx_bitcount <= 1'd0;
			end
		end else begin
			if (uart_phy_uart_clk_rxen) begin
				uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1);
				if ((uart_phy_rx_bitcount == 1'd0)) begin
					if (uart_phy_rx) begin
						uart_phy_rx_busy <= 1'd0;
					end
				end else begin
					if ((uart_phy_rx_bitcount == 4'd9)) begin
						uart_phy_rx_busy <= 1'd0;
						if (uart_phy_rx) begin
							uart_phy_source_payload_data <= uart_phy_rx_reg;
							uart_phy_source_stb <= 1'd1;
						end
					end else begin
						uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]};
					end
				end
			end
		end
		if (uart_phy_rx_busy) begin
			{uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= (uart_phy_phase_accumulator_rx + uart_phy_storage);
		end else begin
			{uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= 32'd2147483648;
		end
		if (uart_tx_clear) begin
			uart_tx_pending <= 1'd0;
		end
		uart_tx_old_trigger <= uart_tx_trigger;
		if (((~uart_tx_trigger) & uart_tx_old_trigger)) begin
			uart_tx_pending <= 1'd1;
		end
		if (uart_rx_clear) begin
			uart_rx_pending <= 1'd0;
		end
		uart_rx_old_trigger <= uart_rx_trigger;
		if (((~uart_rx_trigger) & uart_rx_old_trigger)) begin
			uart_rx_pending <= 1'd1;
		end
		if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
			uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
		end
		if (uart_tx_fifo_do_read) begin
			uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
		end
		if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
			if ((~uart_tx_fifo_do_read)) begin
				uart_tx_fifo_level <= (uart_tx_fifo_level + 1'd1);
			end
		end else begin
			if (uart_tx_fifo_do_read) begin
				uart_tx_fifo_level <= (uart_tx_fifo_level - 1'd1);
			end
		end
		if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
			uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
		end
		if (uart_rx_fifo_do_read) begin
			uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
		end
		if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
			if ((~uart_rx_fifo_do_read)) begin
				uart_rx_fifo_level <= (uart_rx_fifo_level + 1'd1);
			end
		end else begin
			if (uart_rx_fifo_do_read) begin
				uart_rx_fifo_level <= (uart_rx_fifo_level - 1'd1);
			end
		end
		if (timer0_en_storage) begin
			if ((timer0_value == 1'd0)) begin
				timer0_value <= timer0_reload_storage;
			end else begin
				timer0_value <= (timer0_value - 1'd1);
			end
		end else begin
			timer0_value <= timer0_load_storage;
		end
		if (timer0_update_value_re) begin
			timer0_value_status <= timer0_value;
		end
		if (timer0_zero_clear) begin
			timer0_zero_pending <= 1'd0;
		end
		timer0_zero_old_trigger <= timer0_zero_trigger;
		if (((~timer0_zero_trigger) & timer0_zero_old_trigger)) begin
			timer0_zero_pending <= 1'd1;
		end
		case (grant)
			1'd0: begin
				if ((~request[0])) begin
					if (request[1]) begin
						grant <= 1'd1;
					end
				end
			end
			1'd1: begin
				if ((~request[1])) begin
					if (request[0]) begin
						grant <= 1'd0;
					end
				end
			end
		endcase
		slave_sel_r <= slave_sel;
		interface0_dat_r <= 1'd0;
		if (csrbank0_sel) begin
			case (interface0_adr[0])
				1'd0: begin
					interface0_dat_r <= csrbank0_out0_w;
				end
			endcase
		end
		if (csrbank0_out0_re) begin
			leds_storage_full[7:0] <= csrbank0_out0_r;
		end
		leds_re <= csrbank0_out0_re;
		interface1_dat_r <= 1'd0;
		if (csrbank1_sel) begin
			case (interface1_adr[4:0])
				1'd0: begin
					interface1_dat_r <= csrbank1_load3_w;
				end
				1'd1: begin
					interface1_dat_r <= csrbank1_load2_w;
				end
				2'd2: begin
					interface1_dat_r <= csrbank1_load1_w;
				end
				2'd3: begin
					interface1_dat_r <= csrbank1_load0_w;
				end
				3'd4: begin
					interface1_dat_r <= csrbank1_reload3_w;
				end
				3'd5: begin
					interface1_dat_r <= csrbank1_reload2_w;
				end
				3'd6: begin
					interface1_dat_r <= csrbank1_reload1_w;
				end
				3'd7: begin
					interface1_dat_r <= csrbank1_reload0_w;
				end
				4'd8: begin
					interface1_dat_r <= csrbank1_en0_w;
				end
				4'd9: begin
					interface1_dat_r <= timer0_update_value_w;
				end
				4'd10: begin
					interface1_dat_r <= csrbank1_value3_w;
				end
				4'd11: begin
					interface1_dat_r <= csrbank1_value2_w;
				end
				4'd12: begin
					interface1_dat_r <= csrbank1_value1_w;
				end
				4'd13: begin
					interface1_dat_r <= csrbank1_value0_w;
				end
				4'd14: begin
					interface1_dat_r <= timer0_eventmanager_status_w;
				end
				4'd15: begin
					interface1_dat_r <= timer0_eventmanager_pending_w;
				end
				5'd16: begin
					interface1_dat_r <= csrbank1_ev_enable0_w;
				end
			endcase
		end
		if (csrbank1_load3_re) begin
			timer0_load_storage_full[31:24] <= csrbank1_load3_r;
		end
		if (csrbank1_load2_re) begin
			timer0_load_storage_full[23:16] <= csrbank1_load2_r;
		end
		if (csrbank1_load1_re) begin
			timer0_load_storage_full[15:8] <= csrbank1_load1_r;
		end
		if (csrbank1_load0_re) begin
			timer0_load_storage_full[7:0] <= csrbank1_load0_r;
		end
		timer0_load_re <= csrbank1_load0_re;
		if (csrbank1_reload3_re) begin
			timer0_reload_storage_full[31:24] <= csrbank1_reload3_r;
		end
		if (csrbank1_reload2_re) begin
			timer0_reload_storage_full[23:16] <= csrbank1_reload2_r;
		end
		if (csrbank1_reload1_re) begin
			timer0_reload_storage_full[15:8] <= csrbank1_reload1_r;
		end
		if (csrbank1_reload0_re) begin
			timer0_reload_storage_full[7:0] <= csrbank1_reload0_r;
		end
		timer0_reload_re <= csrbank1_reload0_re;
		if (csrbank1_en0_re) begin
			timer0_en_storage_full <= csrbank1_en0_r;
		end
		timer0_en_re <= csrbank1_en0_re;
		if (csrbank1_ev_enable0_re) begin
			timer0_eventmanager_storage_full <= csrbank1_ev_enable0_r;
		end
		timer0_eventmanager_re <= csrbank1_ev_enable0_re;
		interface2_dat_r <= 1'd0;
		if (csrbank2_sel) begin
			case (interface2_adr[2:0])
				1'd0: begin
					interface2_dat_r <= uart_rxtx_w;
				end
				1'd1: begin
					interface2_dat_r <= csrbank2_txfull_w;
				end
				2'd2: begin
					interface2_dat_r <= csrbank2_rxempty_w;
				end
				2'd3: begin
					interface2_dat_r <= uart_status_w;
				end
				3'd4: begin
					interface2_dat_r <= uart_pending_w;
				end
				3'd5: begin
					interface2_dat_r <= csrbank2_ev_enable0_w;
				end
			endcase
		end
		if (csrbank2_ev_enable0_re) begin
			uart_storage_full[1:0] <= csrbank2_ev_enable0_r;
		end
		uart_re <= csrbank2_ev_enable0_re;
		interface3_dat_r <= 1'd0;
		if (csrbank3_sel) begin
			case (interface3_adr[1:0])
				1'd0: begin
					interface3_dat_r <= csrbank3_tuning_word3_w;
				end
				1'd1: begin
					interface3_dat_r <= csrbank3_tuning_word2_w;
				end
				2'd2: begin
					interface3_dat_r <= csrbank3_tuning_word1_w;
				end
				2'd3: begin
					interface3_dat_r <= csrbank3_tuning_word0_w;
				end
			endcase
		end
		if (csrbank3_tuning_word3_re) begin
			uart_phy_storage_full[31:24] <= csrbank3_tuning_word3_r;
		end
		if (csrbank3_tuning_word2_re) begin
			uart_phy_storage_full[23:16] <= csrbank3_tuning_word2_r;
		end
		if (csrbank3_tuning_word1_re) begin
			uart_phy_storage_full[15:8] <= csrbank3_tuning_word1_r;
		end
		if (csrbank3_tuning_word0_re) begin
			uart_phy_storage_full[7:0] <= csrbank3_tuning_word0_r;
		end
		uart_phy_re <= csrbank3_tuning_word0_re;
	end
	regs0 <= serial_rx;
	regs1 <= regs0;
end

lm32_cpu #(
	.eba_reset(32'h00000000)
) lm32_cpu (
	.D_ACK_I(dbus_ack),
	.D_DAT_I(dbus_dat_r),
	.D_ERR_I(dbus_err),
	.D_RTY_I(1'd0),
	.I_ACK_I(ibus_ack),
	.I_DAT_I(ibus_dat_r),
	.I_ERR_I(ibus_err),
	.I_RTY_I(1'd0),
	.clk_i(sys_clk),
	.interrupt(interrupt),
	.rst_i(sys_rst),
	.D_ADR_O(d_adr_o),
	.D_BTE_O(dbus_bte),
	.D_CTI_O(dbus_cti),
	.D_CYC_O(dbus_cyc),
	.D_DAT_O(dbus_dat_w),
	.D_SEL_O(dbus_sel),
	.D_STB_O(dbus_stb),
	.D_WE_O(dbus_we),
	.I_ADR_O(i_adr_o),
	.I_BTE_O(ibus_bte),
	.I_CTI_O(ibus_cti),
	.I_CYC_O(ibus_cyc),
	.I_DAT_O(ibus_dat_w),
	.I_SEL_O(ibus_sel),
	.I_STB_O(ibus_stb),
	.I_WE_O(ibus_we)
);

reg [31:0] mem[0:8191];
reg [31:0] memdat;
always @(posedge sys_clk) begin
	memdat <= mem[rom_adr];
end

assign rom_dat_r = memdat;

initial begin
	$readmemh("mem.init", mem);
end

reg [31:0] mem_1[0:1023];
reg [9:0] memadr;
always @(posedge sys_clk) begin
	if (sram_we[0])
		mem_1[sram_adr][7:0] <= sram_dat_w[7:0];
	if (sram_we[1])
		mem_1[sram_adr][15:8] <= sram_dat_w[15:8];
	if (sram_we[2])
		mem_1[sram_adr][23:16] <= sram_dat_w[23:16];
	if (sram_we[3])
		mem_1[sram_adr][31:24] <= sram_dat_w[31:24];
	memadr <= sram_adr;
end

assign sram_dat_r = mem_1[memadr];

reg [31:0] mem_2[0:4095];
reg [11:0] memadr_1;
always @(posedge sys_clk) begin
	if (main_ram_we[0])
		mem_2[main_ram_adr][7:0] <= main_ram_dat_w[7:0];
	if (main_ram_we[1])
		mem_2[main_ram_adr][15:8] <= main_ram_dat_w[15:8];
	if (main_ram_we[2])
		mem_2[main_ram_adr][23:16] <= main_ram_dat_w[23:16];
	if (main_ram_we[3])
		mem_2[main_ram_adr][31:24] <= main_ram_dat_w[31:24];
	memadr_1 <= main_ram_adr;
end

assign main_ram_dat_r = mem_2[memadr_1];

reg [8:0] storage[0:15];
reg [3:0] memadr_2;
always @(posedge sys_clk) begin
	if (uart_tx_fifo_wrport_we)
		storage[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
	memadr_2 <= uart_tx_fifo_wrport_adr;
end

always @(posedge sys_clk) begin
end

assign uart_tx_fifo_wrport_dat_r = storage[memadr_2];
assign uart_tx_fifo_rdport_dat_r = storage[uart_tx_fifo_rdport_adr];

reg [8:0] storage_1[0:15];
reg [3:0] memadr_3;
always @(posedge sys_clk) begin
	if (uart_rx_fifo_wrport_we)
		storage_1[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
	memadr_3 <= uart_rx_fifo_wrport_adr;
end

always @(posedge sys_clk) begin
end

assign uart_rx_fifo_wrport_dat_r = storage_1[memadr_3];
assign uart_rx_fifo_rdport_dat_r = storage_1[uart_rx_fifo_rdport_adr];

// synthesis attribute shreg_extract of regs0 is no
// synthesis attribute shreg_extract of regs1 is no
// synthesis attribute register_balancing of regs0 is no
// synthesis attribute register_balancing of regs1 is no
endmodule