Icestorm PLL

gen.v

/* Machine-generated using Migen */
module top(
	output user_led,
	output user_led_1,
	output user_led_2,
	output user_led_3,
	output user_led_4,
	input clk12
);

reg ready = 1'd0;
reg [3:0] rot = 1'd0;
reg [23:0] divider = 1'd0;
wire D1;
wire D2;
wire D3;
wire D4;
wire D5;
wire pll_outg;
wire pll_out;
wire lock;
wire sys_clk;
reg sys_rst = 1'd0;
wire gen_clk;
reg gen_rst = 1'd0;

// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign user_led = D1;
assign user_led_1 = D2;
assign user_led_2 = D3;
assign user_led_3 = D4;
assign user_led_4 = lock;
assign sys_clk = clk12;
assign D1 = rot[0];
assign D2 = rot[1];
assign D3 = rot[2];
assign D4 = rot[3];
assign D5 = 1'd1;

always @(posedge gen_clk) begin
	if (gen_rst) begin
		ready <= 1'd0;
		rot <= 1'd0;
		divider <= 1'd0;
	end else begin
		if (ready) begin
			if ((divider == 24'd11999999)) begin
				divider <= 1'd0;
				rot <= {rot[2:0], rot[3]};
			end else begin
				divider <= (divider + 1'd1);
			end
		end else begin
			ready <= 1'd1;
			rot <= 1'd1;
			divider <= 1'd0;
		end
	end
end

SB_PLL40_CORE #(
	.DIVF(7'd79),
	.DIVQ(3'd4),
	.DIVR(1'd0),
	.ENABLE_ICEGATE(1'd0)
) SB_PLL40_CORE (
	.BYPASS(1'd0),
	.DYNAMICDELAY(8'd0),
	.EXTFEEDBACK(1'd0),
	.LATCHINPUTVALUE(1'd0),
	.REFERENCECLK(sys_clk),
	.RESETB((~sys_rst)),
	.LOCK(lock),
	.PLLOUTCORE(pll_out),
	.PLLOUTGLOBAL(pll_outg)
);

SB_GB SB_GB(
	.USER_SIGNAL_TO_GLOBAL_BUFFER(pll_outg),
	.GLOBAL_BUFFER_OUTPUT(gen_clk)
);

endmodule