simple vhdl calculator

binary_calc.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity binary_calc is
    port (
        input1: in std_logic_vector(4 downto 0); -- first 5-bit input number
        input2: in std_logic_vector(4 downto 0); -- second 5-bit input number
        
        op: in std_logic; -- concatenation of button values: add, subtract
        
        result: out std_logic_vector(5 downto 0); -- 6-bit output
        
        number_leds: out std_logic_vector(15 downto 0)
    );
end binary_calc;

architecture binary_calc_behaviour of binary_calc is
    signal input1_6: std_logic_vector(5 downto 0);
    signal input2_6: std_logic_vector(5 downto 0);
begin
    input1_6 <= '0' & input1;
    input2_6 <= '0' & input2;
    
    compute: process (input1, input2, op)
    begin
        --case op is
        --    when '1' =>
        if op = '1' then
                result <= std_logic_vector(unsigned(input1_6) + unsigned(input2_6));
        end if;
        --end case;
    end process compute;
    -- dataflow for leds
    number_leds <= input1 & input2 & result;
end binary_calc_behaviour;

binary_calc_test.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- test entities are empty
entity binary_calc_test is
end binary_calc_test;

architecture Behavioral of binary_calc_test is
    component binary_calc
        port (
            input1: in std_logic_vector(4 downto 0); -- first 5-bit input number
            input2: in std_logic_vector(4 downto 0); -- second 5-bit input number
            
            op: in std_logic; -- addition button
            
            result: out std_logic_vector(5 downto 0); -- 6-bit output
            
            number_leds: out std_logic_vector(15 downto 0)
        );
    end component;
    
    signal input1: std_logic_vector(4 downto 0) := "00010";
    signal input2: std_logic_vector(4 downto 0) := "01010";
    signal op: std_logic := '0';
    
    signal number_leds: std_logic_vector(15 downto 0) := "0000000000000000";

begin
    UUT: binary_calc
    PORT MAP (
        input1 => input1,
        input2 => input2,
        op => op,
        number_leds => number_leds
    );
    
    op_trigger: process
    begin
        wait for 200 ns;
        op <= '1';
        wait for 200 ns;
        op <= '0';
        wait for 100 ns;
        input1 <= "00100";
        input2 <= "10010";
        wait for 100ns;
        op <= '1';
        wait;
    end process op_trigger;
end Behavioral;