| SoC | Kernel driver | VPU IP | Clock | Encode | Decode |
|---|---|---|---|---|---|
| T20 | soc_vpu + jz_nvpu |
NVPU (monolithic) | 333 MHz | H.264, JPEG | H.264, JPEG |
| T21 | soc_vpu + helix |
Helix (H.264+JPEG enc/dec) | 350 MHz | H.264, JPEG | H.264, JPEG |
| T23 | soc_vpu + helix (+IVDC) |
Helix (H.264+JPEG enc/dec) | 450 MHz | H.264, JPEG | H.264, JPEG |
| T30 | soc_vpu + helix + radix |
Helix (H.264+JPEG) + Radix (H.265) | 350 MHz | H.264, H.265, JPEG | H.264, H.265, JPEG |
| T32 | ingenic_vpu + helix + radix |
JPEG engine + Hera (unified H.264+H.265+JPEG) | 500 MHz | H.264, H.265, JPEG | H.264, H.265, JPEG |
| T33 | ingenic_vpu + helix + radix |
JPEG engine + Hera (unified H.264+H.265+JPEG) | 500 MHz | H.264, H.265, JPEG | H.264, H.265, JPEG |
| T31 | avpu.ko (Allegro) |
Allegro AVPU | 400-700 MHz | H.264, H.265, JPEG | H.264, H.265, JPEG |
| T40 | avpu.ko (Allegro EL150) |
Allegro EL150 | 400-700 MHz | H.264, H.265, JPEG | H.264, H.265, JPEG |
| T41 | avpu.ko (Allegro EL200) + helix |
Allegro EL200 + IVDC (JPEG) | 400-700 MHz | H.264, H.265, JPEG | H.264, H.265, JPEG |
| A1 | ingenic_vpu + helix |
VC8000D (decode) + JPEG engine | (gate only) | JPEG only | H.264, H.265, JPEG |
- T20/T21/T30 helix+radix are the same IP, just hardcoded conservatively at 333-350 MHz
- T23 runs at 450 MHz for the same helix IP
- T32/T33 are not the same; "radix" is really Hera, a unified next-gen block with 20 sub-blocks (vs 16), and "helix" is now just a dedicated JPEG accelerator
- T31/T40/T41 uses Allegro IP with configurable clocks
- A1 uses Verisilicon VC8000D for decode