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gtxaspec / ingenic-t-series-encoder.md
Created April 27, 2026 10:57
ingenic encoder blocks
SoC Kernel driver VPU IP Clock Encode Decode
T20 soc_vpu + jz_nvpu NVPU (monolithic) 333 MHz H.264, JPEG H.264, JPEG
T21 soc_vpu + helix Helix (H.264+JPEG enc/dec) 350 MHz H.264, JPEG H.264, JPEG
T23 soc_vpu + helix (+IVDC) Helix (H.264+JPEG enc/dec) 450 MHz H.264, JPEG H.264, JPEG
T30 soc_vpu + helix + radix Helix (H.264+JPEG) + Radix (H.265) 350 MHz H.264, H.265, JPEG H.264, H.265, JPEG
T32 ingenic_vpu + helix + radix JPEG engine + Hera (unified H.264+H.265+JPEG) 500 MHz H.264, H.265, JPEG H.264, H.265, JPEG

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@gtxaspec
gtxaspec / d1_t32.md
Last active March 16, 2026 06:34
cinnado d1 t32 
U-Boot 2013.07-H20250211a (Jun 16 2025 - 19:02:22)

apll_freq = 900000000 
mpll_freq = 1200000000 
vpll_freq = 1188000000

sdram init start
DDR clk rate 600000000
80000e4c 00000000 00000000
@gtxaspec
gtxaspec / thingino-todo.md
Last active April 4, 2026 05:51
thingino todo

-- buildroot --
-jX doesn't work as make arguments
cant delete parent folder due to chmod -R a-w $(BR2_EXTERNAL)/buildroot in makefile running make is very slow, randomly, possibly not using jobserver
add build time to finalize screen at the end of the build? update make edit, to work with the new config file format
buildroot sysupgrade forces remap, this should not be enforced, optional.

-- menuconfig --
image sensor qty should be a menu, with 1-4, not a text box

@gtxaspec
gtxaspec / ingenic-soc.md
Created February 28, 2026 03:24
ingenic t23 / t33 / t32pro

Ingenic SoC Comparison: T23 / T33 / T32Pro Series

1.1 Processor Cores and AI Computing Power

Technical Parameters T23 Series T33 Series T32Pro Series
CPU Architecture Xburst® 1, MIPS32 ISA Xburst® 1, MIPS32 ISA + SIMD128 instruction set Xburst® 1, MIPS32 ISA + SIMD128 instruction set
CPU Clock Speed 1.2 GHz ~ 1.4 GHz 1.0 GHz 1.2 GHz
Cache Configuration 16K I-Cache + 16K D-Cache, 64KB L2 Cache 32KB I-Cache + 32KB D-Cache, 128KB L2 Cache 32KB I-Cache + 32KB D-Cache, 128KB L2 Cache
MCU Configuration 600 MHz RISC-V coprocessor, supporting RV32IMC instruction set 600 MHz RISC-V coprocessor, supporting RV32IMC instruction set 600 MHz RISC-V coprocessor, supporting RV32IMC instruction set
@gtxaspec
gtxaspec / esp32-c6-rcp-how-to.md
Last active April 16, 2026 16:20
ESP32-C6 RCP how to

ESP32-C6 as OpenThread RCP - Setup Guide

Here's how to flash your ESP32-C6 to work as an RCP (Radio Co-Processor) with Home Assistant's OpenThread Border Router add-on.

Step 1: Clone and Setup ESP-IDF

mkdir ~/esp-openthread && cd ~/esp-openthread
git clone -b v5.4.2 --recursive https://github.com/espressif/esp-idf.git
cd esp-idf
@gtxaspec
gtxaspec / gist:d63d151ed0871fca120e908fcdba43f6
Last active February 19, 2026 23:14
IR pronto codes
LG tv:
Power
0000 006D 0022 0000 015B 00AE 0015 0016 0015 0017 0015 0041 0014 0017 0014 0017 0014 0017 0015 0016 0015 0016 0014 0043 0015 0041 0014 0017 0014 0042 0015 0042 0014 0041 0015 0041 0015 0041 0015 0016 0015 0016 0015 0016 0014 0043 0015 0016 0014 0017 0014 0017 0015 0016 0015 0042 0014 0043 0014 0043 0014 0017 0014 0043 0014 0041 0015 0042 0016 0041 0014 0180
Input
0000 006D 0022 0000 015B 00AC 0015 0017 0014 0016 0015 0043 0014 0017 0014 0017 0014 0016 0015 0017 0014 0017 0014 0043 0014 0043 0014 0016 0015 0043 0013 0042 0015 0041 0015 0041 0014 0043 0014 0043 0014 0043 0014 0017 0014 0043 0014 0017 0014 0016 0015 0017 0014 0016 0015 0017 0014 0017 0014 0041 0015 0016 0015 0041 0015 0041 0015 0041 0015 0041 0015 0180 0000 006D 0002 0000 015B 0009 0062 0180
Exit
0000 006D 0022 0000 015A 00AE 0015 0017 0014 0017 0014 0043 0014 0017 0014 0017 0014 0017 0014 0017 0014 0016 0015 0041 0015 0041 0015 0016 0014 0043 0014 0043 0014 0043 0015 0042 0014 0043 0013 0041 0015 0041 0015 0016 0015 0041 0014
@gtxaspec
gtxaspec / wansview-q5.md
Created March 25, 2025 18:39
wansview q5 t23 bootlog 
[root@Ingenic-uc1_1:~]#         cat /sys/kernel/debug/gpio
GPIOs 0-31, GPIO A:
 gpio-6   (sysfs               ) out hi
 gpio-18  (sc2337p_reset       ) out hi

GPIOs 32-63, GPIO B:
 gpio-38  (gpioCtrl            ) in  hi
 gpio-39  (gpioCtrl            ) out hi
 gpio-40  (gpioCtrl            ) out lo
@gtxaspec
gtxaspec / a1n_nvr_stock_bootlog.md
Created March 12, 2025 02:42
A1N NVR bootlog 
U-Boot SPL 2013.07 (Aug 01 2024 - 11:20:18)
chip type is A1N

apll_freq = 1104000000 
mpll_freq = 1500000000 
vpll_freq = 1200000000 
epll_freq = 1500000000
cpu clk source: apll
ddr clk source: mpll
@gtxaspec
gtxaspec / wuuk_0910_t41_bootlog.md
Created February 27, 2025 03:38
wuuk 0910 bootlog 

U-Boot SPL 2013.07 (Sep 14 2023 - 13:47:16)
Board info: T41NQ

apll_freq = 1008000000 
mpll_freq = 1200000000 
vpll_freq = 1188000000 
sdram init start
DDR clk rate 600000000
@gtxaspec
gtxaspec / vanhua-t40-nand.md
Created January 31, 2025 05:45
vanhua t40 nand 
isvp_t40# printenv
baudrate=115200
bootargs=console=ttyS1,115200n8 mem=128M@0x0 nmem=28M@0x8000000 rmem=100M@0x9C00000 ip=off root=/dev/ram rw rdinit=/linuxrc mtdparts=sfc_nand:1M(uboot),1M(factory),8M(config),6M(kernel),28M(appfs),84M(smart)
bootcmd=nand read 0x80600000 0xa00000 0x600000;bootm 0x80600000
bootdelay=1
ethact=Jz4775-9161
ethaddr=be:60:75:4e:16:3e
ipaddr=169.254.118.188
loads_echo=1