Concat converts to VHDL with no explicit unsign

no_converted_unsign_with_concat.py

from myhdl import *

def twiddler(sig_in, sig_out, clock, reset):

    concat_sig_in = ConcatSignal(sig_in(5, 0), intbv(0)[5:])

    @always_seq(clock.posedge, reset=reset)
    def twiddle():
        sig_out.next = concat_sig_in.signed()

    return twiddle

clock  = Signal(bool(0))
reset = ResetSignal(0, active=1, async=False)

signal_in = Signal(intbv(0, min=-511, max=512))
signal_out = Signal(intbv(0, min=-511, max=512))

toVHDL(twiddler, signal_in, signal_out, clock, reset)

The above outputs the following VHDL:

-- File: twiddler.vhd
-- Generated by MyHDL 0.9.dev0
-- Date: Wed May 27 12:15:24 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity twiddler is
    port (
        sig_in: in signed (9 downto 0);
        sig_out: out signed (9 downto 0);
        clock: in std_logic;
        reset: in std_logic
    );
end entity twiddler;


architecture MyHDL of twiddler is





signal concat_sig_in: unsigned(9 downto 0);

begin


concat_sig_in(10-1 downto 5) <= signal_in(5-1 downto 0);
concat_sig_in(5-1 downto 0) <= "00000";


TWIDDLER_TWIDDLE: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            sig_out <= to_signed(0, 10);
        else
            sig_out <= signed(concat_sig_in);
        end if;
    end if;
end process TWIDDLER_TWIDDLE;

end architecture MyHDL;

Notice that the assignment concat_sig_in(10-1 downto 5) <= signal_in(5-1 downto 0); has two issues.

1. signal_in doesn't actually exist except as a name in the original python file.
2. signal_in(5-1 downto 0) should be converted to be unsigned in order that Vivado doesn't throw an error. Whether this is universal or standard I don't know (the VHDL spec is not exactly easy to parse).

Workaround:

def twiddler(sig_in, sig_out, clock, reset):

    unsigned_sig_in = Signal(intbv(0)[len(sig_in):])
    concat_sig_in = ConcatSignal(unsigned_sig_in(5, 0), intbv(0)[5:])

    @always_comb
    def assignments():
        unsigned_sig_in.next = sig_in

    @always_seq(clock.posedge, reset=reset)
    def twiddle():
        sig_out.next = concat_sig_in.signed()

    return twiddle, assignments