Concat converts to VHDL with no explicit unsign

no_converted_unsign_with_concat.py

from myhdl import *

def twiddler(sig_in, sig_out, clock, reset):

    concat_sig_in = ConcatSignal(sig_in(5, 0), intbv(0)[5:])

    @always_seq(clock.posedge, reset=reset)
    def twiddle():
        sig_out.next = concat_sig_in.signed()

    return twiddle

clock  = Signal(bool(0))
reset = ResetSignal(0, active=1, async=False)

signal_in = Signal(intbv(0, min=-511, max=512))
signal_out = Signal(intbv(0, min=-511, max=512))

toVHDL(twiddler, signal_in, signal_out, clock, reset)

Workaround:

def twiddler(sig_in, sig_out, clock, reset):

    unsigned_sig_in = Signal(intbv(0)[len(sig_in):])
    concat_sig_in = ConcatSignal(unsigned_sig_in(5, 0), intbv(0)[5:])

    @always_comb
    def assignments():
        unsigned_sig_in.next = sig_in

    @always_seq(clock.posedge, reset=reset)
    def twiddle():
        sig_out.next = concat_sig_in.signed()

    return twiddle, assignments