crc32_top.v

`default_nettype none
module crc32_top (
    input clk, input rst,
    input [7:0] data,
    output [31:0] state,
);
    reg [31:0] state_reg;
    wire [31:0] state_next;

    crc32 crc32 (
        .data_in(data),
        .state_in(state_reg),
        .state_out(state_next),
    );

    assign state = state_reg;

    always @(posedge clk) if(rst) begin
        state_reg <= 32'hffffffff;
    end else begin
        state_reg <= state_next;
    end

endmodule