test2.v

module first_cyclone(
	input wire SW_0,
	input wire clk_50,
	
	output wire LED_1,
	output wire LED_2,
	output wire LED_3,
	output wire LED_4,
	output wire LED_5,
	output wire LED_6,
	output wire LED_7,
	output wire LED_8
);


reg [7:0] counter;
reg [31:0] pll_counter;
assign {LED_8, LED_7, LED_6, LED_5, LED_4, LED_3, LED_2, LED_1 } = counter;
wire clk0;
pll pll_0(clk_50, , clk0);


always @(posedge clk0)
begin
	if (SW_0 == 1'b0) begin
		if (pll_counter == 1000000) begin
			counter <= counter + 1'b1;
			pll_counter <= 0;
		end
		else
			pll_counter <= pll_counter + 1'b1;
	end
end


endmodule