first.v

module first(
	input wire SW_0,
	
	output wire LED_1,
	output wire LED_2,
	output wire LED_3,
	output wire LED_4,
	output wire LED_5,
	output wire LED_6,
	output wire LED_7,
	output wire LED_8
);

reg [7:0] counter;
assign {LED_8, LED_7, LED_6, LED_5, LED_4, LED_3, LED_2, LED_1 } = counter;


always @(posedge SW_0)
begin
	counter <= counter + 1'b1;
end


endmodule