ram.py

#!/usr/bin/env python
# coding=utf-8

from myhdl import *

@block
def RAM(dout, din, raddr,waddr, we, clk,addr_width=8, data_width=24):

    """  Ram model """
    mem = [Signal(intbv(0)[data_width:]) for i in range(int(2**addr_width))]
    read_addr=Signal(intbv(0)[addr_width:])

    @always_comb
    def out():

        dout.next=mem[read_addr]

    @always(clk.posedge)
    def write():

        read_addr.next=raddr
        if we:
            mem[waddr].next = din


    return instances()