mul.py

from myhdl import *



def mul(ina,inb,out1,clk,reset,width=8):

  ina_reg,inb_reg=[intbv(0,-2**width,2**(width-1)) for i in range(2)]
  out_reg=intbv(0,-2**(2*width),2**(2*width-1))
  @always_seq(clk.posedge, reset=reset)
  def logic():
      ina_reg=ina
      inb_reg=inb
      out_reg=intbv(ina_reg*inb_reg,-2**(2*width),2**(2*width-1))
      out1.next=out_reg

  return logic

width=8
ina,inb=[Signal(intbv(0,-2**width,2**(width-1))) for i in range(2)]
out1=Signal(intbv(0,-2**(2*width),2**(2*width-1)))
clk = Signal(bool(0))
reset = ResetSignal(1, active=1, async=True)
toVHDL(mul,ina,inb,out1,clk,reset)

mul.vhd

-- File: mul.vhd
-- Generated by MyHDL 0.9.0
-- Date: Wed Jan 20 15:39:39 2016


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity mul is
    port (
        ina: in signed (8 downto 0);
        inb: in signed (8 downto 0);
        out1: out signed (16 downto 0);
        clk: in std_logic;
        reset: in std_logic
    );
end entity mul;


architecture MyHDL of mul is


constant width: integer := 8;




begin





MUL_LOGIC: process (clk, reset) is
    variable inb_reg: signed(8 downto 0);
    variable out_reg: signed(16 downto 0);
    variable ina_reg: signed(8 downto 0);
begin
    if (reset = '1') then
        out1 <= to_signed(0, 17);
    elsif rising_edge(clk) then
        ina_reg := ina;
        inb_reg := inb;
        out_reg := to_signed((ina_reg * inb_reg), 17);
        out1 <= out_reg;
    end if;
end process MUL_LOGIC;

end architecture MyHDL;

With hindsight you'd better specify the widths as follows:

width = 9
ina, inb = [Signal(intbv(0, -2**(width-1), 2**(width-1))) for _ in range(2)]
out1 = Signal(intbv(0, -2**(2*width-1), 2**(2*width-1)))

This is easier to understand (IMHO).