[riscv-isa-sim] Simple test case for RISC-V vector crypto unaligned LMUL register indices

vcrypto-lmul-alignment-test-case.c

#include <stdio.h>

// How to build:
//   riscv64-unknown-elf-gcc  -march=rv64gcv_zvkned_zvksed_zvkg_zvknhb_zvksh_zvl128b vcrypto-lmul-alignment-test-case.c
// How to execute:
//   spike --isa=rv64gcv_zvbc_zicntr_zihpm_zvkned_zvksed_zvkg_zvknhb_zvksh_zvl128b <pk-image> a.out


// This program aims at demonstrating that spike is flawed when
// it comes to executing vector crypto instructions with invalid register
// index alignments with respect to LMUL
int main(void) {
  asm volatile (
    // setting LMUL=4
    "vsetivli x1, 16, e32, m4, tu, mu\n"
    // Zvkned
    "vaesdf.vv v20, v11\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vaesdf.vv v21, v8\n" // <=== expected to trap because v21 is not aligned to LMUL=4 
    "vaesdm.vv v20, v11\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vaesdm.vv v21, v8\n" // <=== expected to trap because v21 is not aligned to LMUL=4 
    "vaesef.vv v20, v11\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vaesef.vv v21, v8\n" // <=== expected to trap because v21 is not aligned to LMUL=4 
    "vaesem.vv v20, v11\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vaesem.vv v21, v8\n" // <=== expected to trap because v21 is not aligned to LMUL=4 
    "vaeskf1.vi v20, v11, 7\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vaeskf1.vi v11, v20, 7\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vaeskf2.vi v20, v11, 7\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vaeskf2.vi v11, v20, 7\n" // <=== expected to trap because v11 is not aligned to LMUL=4 

    // The following .vs variants should fail because vd is not LMUL aligned
    "vaesdf.vs v17, v11\n"
    "vaesdm.vs v17, v11\n"
    "vaesef.vs v17, v11\n"
    "vaesem.vs v17, v11\n"

    // the following .vs variant should work (but spec is not clear on this)
    "vaesdf.vs v20, v11\n"
    "vaesdm.vs v20, v11\n"
    "vaesef.vs v20, v11\n"
    "vaesem.vs v20, v11\n"
    "vaesz.vs v20, v11\n"
    
    // Zvksed
    "vsm4k.vi v20, v11, 7\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vsm4k.vi v11, v20, 7\n" // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vsm4r.vv v20, v11\n"    // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vsm4r.vv v11, v20\n"    // <=== expected to trap because v11 is not aligned to LMUL=4 
    "vsm4r.vs v17, v11\n"    // <=== expected to trap because vd=v17 is not aligned to LMUL=4 

    // Zvkg
    // setting LMUL=4
    "vsetivli x1, 16, e32, m4, tu, mu\n"
    "vgmul.vv v17, v8\n"
    "vgmul.vv v8, v11\n"
    "vghsh.vv v17, v24, v8\n"
    "vghsh.vv v24, v17, v8\n"
    "vghsh.vv v8, v24, v17\n"

    // Zvknha
    // setting LMUL=4
    "vsetivli x1, 16, e32, m4, tu, mu\n"
    "vsha2cl.vv v17, v24, v8\n"
    "vsha2cl.vv v24, v17, v8\n"
    "vsha2cl.vv v24, v8, v17\n"
    "vsha2ch.vv v17, v24, v8\n"
    "vsha2ch.vv v24, v17, v8\n"
    "vsha2ch.vv v24, v8, v17\n"
    "vsha2ms.vv v17, v24, v8\n"
    "vsha2ms.vv v24, v17, v8\n"
    "vsha2ms.vv v24, v8, v17\n"

    // Zvknhb
    // setting LMUL=4
    "vsetivli x1, 8, e64, m4, tu, mu\n"
    "vsha2cl.vv v17, v24, v8\n"
    "vsha2cl.vv v24, v17, v8\n"
    "vsha2cl.vv v24, v8, v17\n"
    "vsha2ch.vv v17, v24, v8\n"
    "vsha2ch.vv v24, v17, v8\n"
    "vsha2ch.vv v24, v8, v17\n"
    "vsha2ms.vv v17, v24, v8\n"
    "vsha2ms.vv v24, v17, v8\n"
    "vsha2ms.vv v24, v8, v17\n"

    // Zvksh
    // setting LMUL=4
    "vsetivli x1, 16, e32, m4, tu, mu\n"
    "vsm3c.vi v17, v24, 8\n"
    "vsm3c.vi v24, v17, 8\n"
    "vsm3me.vv v24, v8, v17\n"
    "vsm3me.vv v17, v24, v8\n"
    "vsm3me.vv v24, v17, v8\n"

    // 
    // "vadd.vv v16, v17, v20\n" <== expected to trap because v17 is not aligned to LMUL=EMUL=4
    :
    :
    : "x1"
  );
  printf("program should have trapped\n.");
  return 0;
}