gistfile1.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mypackage.all;

entity ftr is
  port (
    clk, reset, t : in  std_logic;
    q             : out std_logic
    ) ;
end entity;  -- ftr

architecture arch of ftr is
  signal i, q_inner : std_logic;
begin
  runner : process(clk)
  begin
    if(clk = '0' and clk'event and reset = '1') then
      i <= '0';
    elsif(reset = '0') then
      i <= q_inner xor t;
    end if;
  end process;
  ss0 : fd port map(clk, i, q_inner);   -- Här är D-vippan
  q <= q_inner;
end architecture;  -- arch