olofk

filesets:
  f1 :
    files : [file1.v : {file_type : verilogSource}]
targets:
  my_target:
    filesets : [f1]
    generate: [preprocess]

generate:
  preprocess:

olofk

{
	"files": [
		{
			"file_type": "verilogSource",
			"is_include_file": false,
			"logical_name": "",
			"name": "../src/fusesoc_utils_blinky_0/blinky.v"
		},
		{
			"file_type": "cppSource",

olofk

module t
  (input a,
   output [3:0] b);

   genvar 	i;
   //generate <== Should be optional for sv vlog2005
   for (i=0 ; i<4 ; i=i+1) begin : genblock
     assign b[i] = a;
   end
   //endgenerate <== Should be optional for sv vlog2005

olofk

import gi
gi.require_version('Gtk', '3.0')
from gi.repository import Gtk
import sys

win = Gtk.Window()
win.connect("destroy", Gtk.main_quit)

store = Gtk.ListStore(int, str, bool)
with open(sys.argv[1]) as f:

olofk

import sys

from migen.genlib.resetsync import AsyncResetSynchronizer

from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard

from litex.soc.cores.timer import Timer

from litex.soc.interconnect.csr import Module, ClockDomain, Signal, Instance
from litex.soc.interconnect.wishbone import CSRBank

olofk

from edalize import get_edatool

file_list = ['a.v', 'b.vhd', 'c.sdc', 'd.tcl']
name = 'myproject'
toplevel = 'mytoplevel'
tool = 'vivado'

#Where to put the output stuff
work_root = 'build'

olofk

`default_nettype none
module wb2axi
  (
   input wire 	      i_clk,
   input wire 	      i_rst,
   input wire [31:0]  i_wb_adr,
   input wire [31:0]  i_wb_dat,
   input wire [3:0]   i_wb_sel,
   input wire 	      i_wb_we,
   input wire 	      i_wb_cyc,

olofk

  always @ (posedge clk)
  begin
   if(write & ~full)
     fifo[write_pointer&{CNT_WIDTH-2{clear}}] <= data_in;
  end
  

  always @ (posedge clk)
  begin
      data_out <= fifo[read_pointer&{CNT_WIDTH-2{clear}}];

olofk

Slack (VIOLATED) :        -3.578ns  (required time - arrival time)
  Source:                 swervolf/rvtop/swerv/lsu/dccm_ctl/Gen_dccm_enable.dccm_data_lo_ff/dout_reg[26]/C
                            (rising edge-triggered cell FDCE clocked by clk50_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            swervolf/rvtop/swerv/dec/instbuff/ib2ff/genblock.dff/dffs/dout_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by clk50_int  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             clk50_int
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            20.000ns  (clk50_int rise@20.000ns - clk50_int rise@0.000ns)
  Data Path Delay:        19.827ns  (logic 3.114ns (15.706%)  route 16.713ns (84.294%))
  Logic Levels:           19  (CARRY4=1 LUT2=2 LUT3=1 LUT4=3 LUT5=3 LUT6=9)

olofk

FROM debian:buster-slim

LABEL Description="SweRVolf image" Vendor="CHIPS Alliance" Version="2019.1"
LABEL maintainer="Olof Kindgren <olof@fossi-foundation.org>"

#wheel??
RUN apt-get update && apt-get --no-install-recommends install -y \
    bzip2 \
    cmake \
    file \