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This document is devoted to derive the filter gates applied on the select lines of a multiplexer before entering the main AND circuit to produce the proper truth table. The document starts first by introducing the preliminaries using a miniaturized model, the 4-to-1 Multiplexer Model, the prototypical model of a MUX circuitry.
English:
For a 4-to-1 Multiplexer case.
Let, $γ$ and $φ$ be symbols designating the select lines of the multiplexer
And, $i$ be the symbols designating the input lines to the multiplexer, and $q$ designate the single output line from the MUX.
; where $n_i$ is the number of the input lines, $n_s$ is the number of select lines, and $n_f$ is the total number of the
filter lines applied to the select lines for each input line.
; where $i_{n_i}$ is the input line at $n_i$, $s_{n_s}$ is the select line at $n_s$, and $f(s)_{n_s}$ is the filter function applied on the select line $s_{n_s}$ at $n_s$.
The quantification formula only holds when the assertion functions hold, and the circuitry selects an input line as an output.