gistfile1.txt

# say u have 3 channels transmitting 4-bit signals 
a = [[1,0,0,1],[1,1,0,0],[1,1,0,1]]
# say u flatten it to get b
b = [1,0,0,1,1,1,0,0,1,1,0,1]
#so when you wish to access signal in 3rd channel you need to
print(a[2])
print(b[4*(2-1):4*(2)])
#now when you just wish to assign channel 2 to 3 and 3 to 2...problem would really start to exponentially increase in 
#flattened part and the point of generalising ND list using flattening seems to be lost...please correct me if i am wrng.. 

So to create a 3 channels transmitting 4-bit signals you'd have:

a = [Signal(intbv(0)[4:]), Signal(intbv(0)[4:]), Signal(intbv(0)[4:])]

no?

Yup, i just skipped the defining signal part..assume the integers to be the values the signal contain...
Also well i dont know whether what i want to do is practically feasible in HDLs ...so please let me know..

What is it you want to do in HDL? That's still not quite clear to me. Perhaps you could have a toy example in valid MyHDL and how you'd like it to work?

The flattening scheme (is different that the unrolling) is reasonable to think about and propose, the good part is you wouldn't need to add lots of additional conversion code, you simply (haha) replace on ND accesses with a flat. The good thing about this approach is you don't is that it will be fairly straightforward in the V* (i.e. which verilog array version do you use).