ravijain056

# say u have 3 channels transmitting 4-bit signals 
a = [[1,0,0,1],[1,1,0,0],[1,1,0,1]]
# say u flatten it to get b
b = [1,0,0,1,1,1,0,0,1,1,0,1]
#so when you wish to access signal in 3rd channel you need to
print(a[2])
print(b[4*(2-1):4*(2)])
#now when you just wish to assign channel 2 to 3 and 3 to 2...problem would really start to exponentially increase in 
#flattened part and the point of generalising ND list using flattening seems to be lost...please correct me if i am wrng.. 

ravijain056

from myhdl import *

def switchchannels(mem2d, q, clk):

    def assign_los(mem1d_a, mem1d_b):
        print(mem1d_a, mem1d_b)
        for i in range(len(mem1d_a)):
            mem1d_a[i].next = mem1d_b[i]
        return mem1d_a
    

ravijain056

from myhdl import *

def switchchannels(mem2d, q, clk):

    def assign_los(mem1d_a, mem1d_b):
        print(mem1d_a, mem1d_b)
        for i in range(len(mem1d_a)):
            mem1d_a[i].next = mem1d_b[i]
        return mem1d_a

ravijain056

from __future__ import absolute_import
import os
path = os.path

from myhdl import *

def ram1(dout, din, addrx, addry, we, clk, depth=128, width=8):
    """ Simple ram model """

    @instance

ravijain056

from random import randint
from myhdl import *

def m_2dlos(clock, reset, x, y, Nrows=4, Mcols=8):

    mem2d = [[Signal(intbv(randint(1, 7689), min=0, max=7690)) 
              for col in range(Mcols)] 
             for row in range(Nrows)]
    rcnt = Signal(modbv(0, min=0, max=4))
    ccnt = Signal(modbv(0, min=0, max=8))

ravijain056

#include <iostream>
using namespace std;

int main() {
    int t;
    cin >> t;
    while(t--) {
        long int cave_size, tractor_size;
        cin >> cave_size >> tractor_size;
        int cave[cave_size][cave_size];

ravijain056

from myhdl import Signal, instances


class A_Interface:
  def __init__(self):
    a = Signal(bool(0)) 
    
class B_Interface:
  def __init__(self):
    b = Signal(bool(0))

ravijain056

from myhdl import Signal, TristateSignal, block, instance, delay, always_comb


@block
def foo(clk, iopin):
    
    tri = Signal(bool(0))
    iopindriver = iopin.driver()
    
    @always_comb

ravijain056

from myhdl import Signal, TristateSignal, block, instance, delay, always_comb, always_seq


@block
def foo(clk, iopin):
    
    tri = Signal(bool(0))
    iopindriver = iopin.driver()
    """
    @always_comb

ravijain056

from myhdl import Signal, block, always_seq, instance, delay


@block
def deadlock():  # not convertible
    sig1 = Signal(bool(0))
    
    @instance
    def initialpush():
        yield delay(10)