Basic usage of a signal in VHDL

sig_example.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sig_example is
 port(
   a1 : in std_logic;
   a2 : in std_logic;
   o1 : out std_logic;
   o2 : out std_logic
  );
end entity;
architecture rtl of sig_example is
  signal my_sig : std_logic; -- creating a signal
begin
  o1 <= a1 or a2;
  my_sig <= a1 and a2;       -- using it as a connection between operation with input ports
  o2 <= not(my_sig);         -- and output port
end rtl;