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smirnovich

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@smirnovich
smirnovich / prior_encod.sv
Last active April 17, 2023 12:17
simple priority encoder on SystemVerilog to check if it is synthesizable in different software
`timescale 1ns / 1ps
module prior_encod(
input logic [11:0] sw,
output logic [3:0] leds
);
always_comb begin
if (sw == 12'b0) begin
leds = 4'b0;
end else begin
@smirnovich
smirnovich / simple_process.vhd
Last active April 2, 2023 15:20
VHDL process block example
library ieee;
use ieee.std_logic_1164.all;
entity simple_process is
port(
cmd : in std_logic;
d1 : in std_logic_vector(3 downto 0);
d2 : in std_logic_vector(3 downto 0);
o1 : out std_logic_vector(3 downto 0)
);
@smirnovich
smirnovich / type_gen.vhd
Created April 2, 2023 12:50
<...>
type t_my_type is (idle, green, yellow, blue);
signal fsm_lights : t_my_type :=idle;
<...>
@smirnovich
smirnovich / testbench.vhd
Created March 24, 2023 09:40
Testbench for demo1
library IEEE;
use IEEE.std_logic_1164.all;
use std.env.stop;
entity testbench is
end entity;
architecture tb of testbench is
@smirnovich
smirnovich / demo1.vhd
Created March 24, 2023 09:22
demo file to test
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity demo1 is
port(
data0 : in std_logic;
data1 : in std_logic_vector(7 downto 0);
data2 : in std_logic_vector(7 downto 0);
my_out : out std_logic_vector(8 downto 0)
@smirnovich
smirnovich / flag_example.vhd
Created March 14, 2023 07:24
VHDL simple arithmetic with sequential logic example
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flag_example is
port(
data : in std_logic_vector(3 downto 0);
flag : in std_logic;
o2 : out std_logic_vector(3 downto 0)
);
end entity;
@smirnovich
smirnovich / sig_seq.vhd
Created March 14, 2023 07:20
VHDL using signal in sequential logic
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sig_seq is
port(
clk : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
o1 : out std_logic
);
@smirnovich
smirnovich / sig_example.vhd
Created March 14, 2023 07:18
Basic usage of a signal in VHDL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sig_example is
port(
a1 : in std_logic;
a2 : in std_logic;
o1 : out std_logic;
o2 : out std_logic
);
@smirnovich
smirnovich / upgraded_trigger.vhd
Last active March 14, 2023 07:16
More advance VHDL trigger with async reset and sync enable
library ieee;
use ieee.std_logic_1164.all;
entity upgraded_trigger is
port(
clk : in std_logic;
rst : in std_logic
d : in std_logic;
en : in std_logic;
q : out std_logic
@smirnovich
smirnovich / simple_trigger.vhd
Last active March 13, 2023 19:49
Simple VHDL trigger
library ieee;
use ieee.std_logic_1164.all;
entity simple_trigger is
port(
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end entity;