VHDL simple arithmetic with sequential logic example

flag_example.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flag_example is
 port(
   data        : in std_logic_vector(3 downto 0);
   flag        : in std_logic;
   o2          : out std_logic_vector(3 downto 0)
  );
end entity;
architecture rtl of flag_example is
  signal my_sig : std_logic_vector(3 downto 0);
begin
  process(clk)
  begin
    if ( rising_edge(clk)) then
      o2 <= my_sig;
      if (flag = '1') then
        my_sig <= std_logic_vector(unsigned(data) + unsigned(my_sig));
      end if;
    end if;
  end process;
end rtl;