VHDL using signal in sequential logic

sig_seq.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sig_seq is
 port(
   clk : in std_logic;
   a1  : in std_logic;
   a2  : in std_logic;
   o1  : out std_logic
  );
end entity;
architecture rtl of sig_example is
  signal my_sig : std_logic;      -- initializing signal
begin
  process(clk)
  begin
    if rising_edge(clk) then
      my_sig <= a1 and a2;        -- both operations are simultaneous for execution
      o1     <= not(my_sig);      -- but they executed only with positive edge of clk
    end if;
  end process;
end rtl;