IR -> IR Optimization -> Code Generation(Register allocation/Instruction selection) Assembly
1.top-of-stack caching (1-TOSCA)
2.init garbage collector
1.similar to C++ inheritance
2.gc in COOL runtime
3.Class Tag, Object Size, Dispatch table pointer (similar to C++ vptr), Dispatch table (similar to C++ vtable)
4.register allocation is Graph coloring
(Linear-Scan Register Allocation
is another way to allocate registers)
1.Three-address code (it doesn't be implemented in this course)
1.it contains a concurrent garbage collector
2.the management of application memory
3.how the program accesses variables, mechanisms for passing parameters between procedures
4.interfacing with the operating system
5.The compiler makes assumptions depending on the specific runtime system to generate correct code.
gc is also part of the program
1.gc in runtime
2.how gc works
3.stack-based virtual machine -> register-based virtual machine (?
4.code generation
4-1. stack based machine
4-2. register based machine
-> register allocation and assignment
-> instruction selection/instruction scheduling
5. how to verify and test compiler?
aarch64 note
SP_EL0
is an alias forSP
. Do not use SP as a general purpose register.Source: https://developer.arm.com/documentation/dui0801/g/Overview-of-AArch64-state/Stack-Pointer-register
.space
The
.skip
and.zero
directives are aliases for the .space directive.label
REF: What is the difference between =label (equals sign) and [label] (brackets) in ARMv6 assembly?
it's not allowed to
mov r0, 0x12345678
(Error: immediate cannot be moved by a single instruction
)system call
read (int) :
0x3f
(63)write (int):
0x40
(64)write (str):
0x40
(64)brk:
0xd6
(214)exit:
0x5d
(93)exception handling
eret
(=rfe
in mips): return from an exceptionVBAR_EL1
(Vector Based Address Registers in EL1)Exception types
The type of exception (SError, FIQ, IRQ, or Synchronous)
CurrentEL bits[3:2] (bit #3 - bit #2)
00 (EL0)
01 (EL1)
10 (EL2)
11 (EL3)
not
e.g. not(0) = not(0x00000000) = 0x11111111 = -1
ldrb