This contains notes about using the Xilinx FPGA development Kintex ku3p ultra scale + development XCKU3P-FFVB676. The branding is Alibaba Cloud with part number AS02MC04.
Read the Device DNA over JTAG and using AMD Device Lookup reports:
| Device | XCKU3P |
| Package-Pin | FFVB676 |
| Revision Code | AAZ |
| SpeedGrade | 1E |
The results of searching for information on AS02MC04.
The following differ about if pcie_perstn_rst is LVCMOS33 or LVCMOS18.
as02mc04_hack is a github project with some board files.
The part specified in the project is xcku3p-ffvb676-2-e, which a faster speed grade 2E than the 1E read via DNA.
The translation of the readme in the project has a title of AS02MC04 Board Reverse Engineering Data which is perhaps why the speed grade is wrong in the project. Not sure if different boards have different speed grade parts fitted.
Commit 65ab096 changed as02mc04/1.0/part0_pins.xml from:
<pin index="94" name="pcie_perstn_rst" iostandard="LVCMOS18" loc="T19"/>To:
<pin index="94" name="pcie_perstn_rst" iostandard="LVCMOS18" loc="A9"/>- Low-cost, high-performance FPGA development tool: XiaoAli board AS02MC04 complete development tutorial [Part 1] - Exploring the unlimited potential of Xilinx Kintex UltraScale+ FPGA This has some images of pin out tables.
- AS02MC04 Development Tutorial for XiaoAli Board [Part 2] - Clock and LED Configuration and Flash Loading Configuration This has some constraints as text. The QSPI is given as MT25QU256, which is the same base part number as used on Notes about XCKU5P PCIE 3.0 QSFP X2
- Xiao Ali Board AS02MC04 Development Tutorial [Part 3] - PCIE 3.0 x8 Interface Development and Speed Test Verification This doesn't contain any additional pin out information.
A copy of the constraints is:
set_property PACKAGE_PIN B11 [get_ports {LED[0]}]
set_property PACKAGE_PIN C11 [get_ports {LED[1]}]
set_property PACKAGE_PIN A10 [get_ports {LED[2]}]
set_property PACKAGE_PIN B10 [get_ports {LED[3]}]
set_property PACKAGE_PIN E18 [get_ports diff_100mhz_clk_p]
set_property IOSTANDARD LVDS [get_ports diff_100mhz_clk_p]
set_property IOSTANDARD LVDS [get_ports diff_100mhz_clk_n]
set_property PACKAGE_PIN A12 [get_ports LED_G]
set_property PACKAGE_PIN A13 [get_ports LED_R]
set_property PACKAGE_PIN B9 [get_ports LED_HEART]
set_property PACKAGE_PIN B12 [get_ports SFP_1_LED]
set_property PACKAGE_PIN C12 [get_ports SFP_2_LED]
#set_property PACKAGE_PIN K7 [get_ports sfp_mgt_clk_p]
set_property PACKAGE_PIN F12 [get_ports SW_RESET]
set_property IOSTANDARD LVCMOS18 [get_ports {LED[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports LED_G]
set_property IOSTANDARD LVCMOS18 [get_ports LED_HEART]
set_property IOSTANDARD LVCMOS18 [get_ports LED_R]
set_property IOSTANDARD LVCMOS18 [get_ports SW_RESET]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_1_LED]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_2_LED]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 31.9 [current_design]Alibaba cloud FPGA: the 200$ Kintex UltraScale+ [Updated] has the same PCIe constraints, in terms of lanes, as https://github.com/TiferKing/as02mc04_hack/blob/main/as02mc04/1.0/part0_pins.xml
1.4. Low-cost, high-performance FPGA development tool: A complete development tutorial for the Alibaba Cloud AS02MC04 board [Part 1]
https://blog.csdn.net/qq_37650251/article/details/145716953 has:
Pin Index Name IO Standard Location Bank
0 diff_100mhz_clk_p LVDS E18 BANK67
1 diff_100mhz_clk_n LVDS D18 BANK67
2 sfp_mgt_clk_p LVDS K7 BANK227
3 sfp_mgt_clk_n LVDS K6 BANK227
4 sfp_1_txn - B6 BANK227
5 sfp_1_txp - B7 BANK227
6 sfp_1_rxn - A3 BANK227
7 sfp_1_rxp - A4 BANK227
8 sfp_2_txn - D6 BANK227
9 sfp_2_txp - D7 BANK227
10 sfp_2_rxn - B1 BANK227
11 sfp_2_rxp - B2 BANK227
12 SFP_1_MOD_DEF_0 LVCMOS18 D14 BANK87
13 SFP_1_TX_FAULT LVCMOS18 B14 BANK87
14 SFP_1_LOS LVCMOS18 D13 BANK87
15 SFP_1_LED LVCMOS18 B12 BANK87
16 SFP_2_MOD_DEF_0 LVCMOS18 E11 BANK86
17 SFP_2_TX_FAULT LVCMOS18 F9 BANK86
18 SFP_2_LOS LVCMOS18 E10 BANK86
19 SFP_2_LED LVCMOS18 C12 BANK87
20 IIC_SDA_SFP_1 LVCMOS18 C14 BANK87
21 IIC_SCL_SFP_1 LVCMOS18 C13 BANK87
22 IIC_SDA_SFP_2 LVCMOS18 D11 BANK86
23 IIC_SCL_SFP_2 LVCMOS18 D10 BANK86
24 IIC_SDA_EEPROM_0 LVCMOS18 G10 BANK86
25 IIC_SCL_EEPROM_0 LVCMOS18 G9 BANK86
26 IIC_SDA_EEPROM_1 LVCMOS18 J15 BANK87
27 IIC_SCL_EEPROM_1 LVCMOS18 J14 BANK87
28 GPIO_LED_R LVCMOS18 A13 BANK87
29 GPIO_LED_G LVCMOS18 A12 BANK87
30 GPIO_LED_H LVCMOS18 B9 BANK86
31 GPIO_LED_1 LVCMOS18 B11 BANK86
32 GPIO_LED_2 LVCMOS18 C11 BANK86
33 GPIO_LED_3 LVCMOS18 A10 BANK86
34 GPIO_LED_4 LVCMOS18 B10 BANK86
35 pcie_mgt_clkn - T6 BANK225
36 pcie_mgt_clkp - T7 BANK225
37 pcie_tx0_n - R4 BANK225
38 pcie_tx1_n - U4 BANK225
39 pcie_tx2_n - W4 BANK225
40 pcie_tx3_n - AA4 BANK225
41 pcie_tx4_n - AC4 BANK224
42 pcie_tx5_n - AD6 BANK224
43 pcie_tx6_n - AE8 BANK224
44 pcie_tx7_n - AF6 BANK224
45 pcie_rx0_n - P1 BANK225
46 pcie_rx1_n - T1 BANK225
47 pcie_rx2_n - V1 BANK225
48 pcie_rx3_n - Y1 BANK225
49 pcie_rx4_n - AB1 BANK224
50 pcie_rx5_n - AD1 BANK224
51 pcie_rx6_n - AE3 BANK224
52 pcie_rx7_n - AF1 BANK224
53 pcie_tx0_p - R5 BANK225
54 pcie_tx1_p - U5 BANK225
55 pcie_tx2_p - W5 BANK225
56 pcie_tx3_p - AA5 BANK225
57 pcie_tx4_p - AC5 BANK224
58 pcie_tx5_p - AD7 BANK224
59 pcie_tx6_p - AE9 BANK224
60 pcie_tx7_p - AF7 BANK224
61 pcie_rx0_p - P2 BANK225
62 pcie_rx1_p - T2 BANK225
63 pcie_rx2_p - V2 BANK225
64 pcie_rx3_p - Y2 BANK225
65 pcie_rx4_p - AB2 BANK224
66 pcie_rx5_p - AD2 BANK224
67 pcie_rx6_p - AE4 BANK224
68 pcie_rx7_p - AF2 BANK224
69 pcie_perstn_rst LVCMOS18 A9 BANK86
https://github.com/fpganinja/taxi/blob/master/src/cndm/board/AS02MC04/fpga/syn/pcie.xdc has pin constraints.
The QSPI has Micron FBGA Code RW170, which is Part Number MT25QU256ABA8ESF-0SIT
Parsing the configuration bitstream read via a FPGA design:
$ xilinx_quad_spi/quad_spi_flasher
Opening device 0000:01:00.0 (10ee:9038) with IOMMU group 0
Enabled bus master for 0000:01:00.0
Warning: Device device 0000:01:00.0 (10ee:9038) has reduced bandwidth
Max width x8 speed 8 GT/s. Negotiated width x8 speed 2.5 GT/s
Displaying information for SPI flash using AS02MC04_dma_stream_crc64 design in PCI device 0000:01:00.0 IOMMU group 0
FIFO depth=256
Flash device : Micron N25Q256A
Manufacturer ID=0x20 Memory Interface Type=0xbb Density=0x19
Flash Size Bytes=33554432 Page Size Bytes=256 Num Address Bytes=4
Successfully parsed bitstream of length 12603672 bytes with 159333 configuration packets
Read 12615680 bytes from SPI flash starting at address 0
Sync word at byte index 0x50
Type 1 packet opcode NOP
Type 1 packet opcode write register BSPI words 0000066C
Type 1 packet opcode write register CMD command BSPI_READ
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register TIMER words 00000000
Type 1 packet opcode write register WBSTAR words 00000000
Type 1 packet opcode write register CMD command NULL
Type 1 packet opcode NOP
Type 1 packet opcode write register CMD command RCRC
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register FAR words 00000000
Type 1 packet opcode write register RBCRC_SW words 00000000
Type 1 packet opcode write register COR0 words 38083FE5
Type 1 packet opcode write register COR1 words 00400000
Type 1 packet opcode write register IDCODE KU3P
Type 1 packet opcode write register CMD command FALL_EDGE
Type 1 packet opcode write register CMD command SWITCH
Type 1 packet opcode NOP
Type 1 packet opcode write register MASK words 00000001
Type 1 packet opcode write register CTL0 words 00000101
Type 1 packet opcode write register MASK words 00001000
Type 1 packet opcode write register CTL1 words 00001000
Type 1 packet opcode NOP (8 consecutive)
Configuration data writes consisting of:
134708 NOPs
11794 FAR writes
318 WCFG commands
318 FDRI writes with a total of 61752 words
58 MFW commands
58 NULL commands
11476 MFWR writes with a total of 160664 words
140 Type 2 packets with a total of 2756892 words
Type 1 packet opcode write register CRC words EEFE3AE6
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register CMD command GRESTORE
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register CMD command DGHIGH_LFRM
Type 1 packet opcode NOP (20 consecutive)
Type 1 packet opcode write register MASK words 00001000
Type 1 packet opcode write register CTL1 words 00000000
Type 1 packet opcode write register CMD command START
Type 1 packet opcode NOP
Type 1 packet opcode write register FAR words 07FC0000
Type 1 packet opcode write register MASK words 00000101
Type 1 packet opcode write register CTL0 words 00000101
Type 1 packet opcode write register CRC words 5FFE959E
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register CMD command DESYNC
Type 1 packet opcode NOP (393 consecutive)
This uses the AS02MC04_dma_stream_crc64 design
The design failed to enumerate on the PCIe bus, over multiple attempts.
Enabled the JTAG debugger in the DMA bridge IP. Failed to obtain any conclusive reason for the failure to enumerate. Sometimes source AS02MC04_dma_stream_crc64/AS02MC04_dma_stream_crc64.gen/sources_1/bd/AS02MC04_dma_stream_crc64/ip/AS02MC04_dma_stream_crc64_xdma_0_0/ip_0/AS02MC04_dma_stream_crc64_xdma_0_0_pcie4_ip/pcie_debugger/test_rd.tcl would result in a AXI timeout being reported (didn't record the exact error).
An Intel DH67BL motherboard with a i5-2310 CPU. Running AlmaLinux 8.10.
The same FPGA design which failed to enumerate in the HP Pavilion 590-p0053na didn't enumerate in this PC.
As per AS02MC04_dma_stream_crc64 in this PC after a VFIO open the link speed trains at 2.5 GT/s rather than the expected 5 GT/s supported by the PC. Same issue as seen with other FPGA boards in the same PC.
Haven't seen pcie_debugger/test_rd.tcl fail with a timeout.
Describes issues with trying to get the PCIe endpoint to enumerate as Gen3 speed x8 width, using the AS02MC04_dma_stream_crc64 design based upon DMA/Bridge Subsystem for PCI Express (4.2)
Started with the following constaints, which match part0_pins.xml:
set_property PACKAGE_PIN P2 [get_ports {pcie_7x_mgt_rxp[0]}]
set_property PACKAGE_PIN T2 [get_ports {pcie_7x_mgt_rxp[1]}]
set_property PACKAGE_PIN V2 [get_ports {pcie_7x_mgt_rxp[2]}]
set_property PACKAGE_PIN Y2 [get_ports {pcie_7x_mgt_rxp[3]}]
set_property PACKAGE_PIN AB2 [get_ports {pcie_7x_mgt_rxp[4]}]
set_property PACKAGE_PIN AD2 [get_ports {pcie_7x_mgt_rxp[5]}]
set_property PACKAGE_PIN AE4 [get_ports {pcie_7x_mgt_rxp[6]}]
set_property PACKAGE_PIN AF2 [get_ports {pcie_7x_mgt_rxp[7]}]This failed to enumerate
An Intel DH67BL motherboard with a i5-2310 CPU.
This enumerated at x8 width. The speed was Gen1 but could be re-trained to Gen2 which is the fastest supported by the CPI.
This enumerated at Gen 3 x4 width.
The slot is x8 width when SSD1 isn't fitted, and the BIOS indicates supports bifurcation as either x8 or x4x4.
Changing the BIOS bifurcation from Auto to x8 still resulted in enumeration at x4 width.
This failed to enumerate.
The slot is Gen3 x16.
This failed to enumerate.
The slot is Gen3 x8, and the BIOS indicates supports bifurcation as either x8 or x4x4.
Rebuilt the AS02MC04_dma_stream_crc64 with modified constraints to reverse all 8 lanes at the FPGA pins, compared to reversed engineered examples. I.e. used:
set_property PACKAGE_PIN P2 [get_ports {pcie_7x_mgt_rxp[7]}]
set_property PACKAGE_PIN T2 [get_ports {pcie_7x_mgt_rxp[6]}]
set_property PACKAGE_PIN V2 [get_ports {pcie_7x_mgt_rxp[5]}]
set_property PACKAGE_PIN Y2 [get_ports {pcie_7x_mgt_rxp[4]}]
set_property PACKAGE_PIN AB2 [get_ports {pcie_7x_mgt_rxp[3]}]
set_property PACKAGE_PIN AD2 [get_ports {pcie_7x_mgt_rxp[2]}]
set_property PACKAGE_PIN AE4 [get_ports {pcie_7x_mgt_rxp[1]}]
set_property PACKAGE_PIN AF2 [get_ports {pcie_7x_mgt_rxp[0]}]With the board fitted into HP Z4 G4 slot switching between two bitstreams repeatidly resulted in:
- With the original lane mapping, did not enumerate
- With the reversed lane mapping, enumerated at x4 width.
When has enumerated with the reversed lane mapping:
[mr_halfword@skylake-alma release]$ identify_pcie_fpga_design/display_identified_pcie_fpga_designs -d 0000:2d:00.0
Opening device 0000:2d:00.0 (10ee:9038) with IOMMU group 25
Enabled bus master for 0000:2d:00.0
Warning: Device device 0000:2d:00.0 (10ee:9038) has reduced bandwidth
Max width x8 speed 8 GT/s. Negotiated width x4 speed 8 GT/s
Design AS02MC04_dma_stream_crc64:
PCI device 0000:2d:00.0 rev 00 IOMMU group 25 physical slot 5-2
DMA bridge bar 2 AXI Stream
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
H2C 1 1 1 64
H2C 2 1 1 64
H2C 3 1 1 64
C2H 0 1 1 64
C2H 1 1 1 64
C2H 2 1 1 64
C2H 3 1 1 64
User access build timestamp : 14332B0F - 02/08/2025 18:44:15
Quad SPI registers at bar 0 offset 0x0
SYSMON registers at bar 0 offset 0x1000
Lane Reversal in the UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213) says when lane reversal is supported.
4.3. Investigation into different FPGA configurations - when configuration memory had design which fails to enumerate
This uses the board in the HP Z4 G4 slot 5.
In the BIOS PCIe related settings are the following:
- System Options -> PCIe Training Reset -> Enable (default was Disable, had enabled it during a previous test)
- Slot Settings -> Slot 5 PCI Express x8
- Option ROM Download -> Enable
- Limit PCIe Speed -> Auto
- Bifurcation -> Auto
- Resizable Bars -> Disable
Due to Windows 11 not booting after update to 24H2 can't boot into Windows to run the tool which saves all settings to a file, and therefore the above settings were checked in the BIOS GUI.
Had previously used the Windows utility to enable hot-plug support on slot 5, which is a setting which isn't visible in the BIOS GUI.
The configurarion memory of the FPGA is from a version of AS02MC04_dma_stream_crc64 with local modifications not under GIT control:
- The red, rather than green, board edge LED indicates the PCIe link is up. That is easier to see as other LEDs on the board are gree.
- The lanes are reversed in the constraints
At power up at PCIe link doesn't come up. There are two root ports, with physical slots 5 and 5-1:
$ dump_info/display_physical_slots
Access method : linux-sysfs
domain=0000 bus=15 dev=00 func=00
vendor_id=10ee (Xilinx Corporation) device_id=7024 (Device 7024)
physical slot: 3-1
domain=0000 bus=2c dev=02 func=00
vendor_id=8086 (Intel Corporation) device_id=2032 (Sky Lake-E PCI Express Root Port C)
physical slot: 6
domain=0000 bus=00 dev=1d func=00
vendor_id=8086 (Intel Corporation) device_id=a298 (200 Series PCH PCI Express Root Port #9)
physical slot: 4
domain=0000 bus=2c dev=03 func=00
vendor_id=8086 (Intel Corporation) device_id=2033 (Sky Lake-E PCI Express Root Port D)
physical slot: 7
domain=0000 bus=2c dev=00 func=00
vendor_id=8086 (Intel Corporation) device_id=2030 (Sky Lake-E PCI Express Root Port A)
physical slot: 5
domain=0000 bus=00 dev=1b func=00
vendor_id=8086 (Intel Corporation) device_id=a2eb (200 Series PCH PCI Express Root Port #21)
physical slot: 8191
domain=0000 bus=2c dev=01 func=00
vendor_id=8086 (Intel Corporation) device_id=2031 (Sky Lake-E PCI Express Root Port B)
physical slot: 5-1
domain=0000 bus=37 dev=00 func=00
vendor_id=10ee (Xilinx Corporation) device_id=7011 (7-Series FPGA Hard PCIe block (AXI/debug))
physical slot: 6-1
domain=0000 bus=14 dev=00 func=00
vendor_id=8086 (Intel Corporation) device_id=2030 (Sky Lake-E PCI Express Root Port A)
physical slot: 3
domain=0000 bus=20 dev=00 func=00
vendor_id=8086 (Intel Corporation) device_id=2030 (Sky Lake-E PCI Express Root Port A)
physical slot: 1
Both root ports for slots 5 and 5-1 have a x4 width.
If boot the FPGA from the configuration memory when Linux is booted the link comes up, as x4 on physical slot 5-2:
$ identify_pcie_fpga_design/display_identified_pcie_fpga_designs
Opening device 0000:15:00.0 (10ee:7024) with IOMMU group 41
Enabled bus master for 0000:15:00.0
Opening device 0000:2d:00.0 (10ee:9038) with IOMMU group 25
Enabled bus master for 0000:2d:00.0
Warning: Device device 0000:2d:00.0 (10ee:9038) has reduced bandwidth
Max width x8 speed 8 GT/s. Negotiated width x4 speed 8 GT/s
Opening device 0000:37:00.0 (10ee:7011) with IOMMU group 86
Enabled bus master for 0000:37:00.0
Design dma_blkram (TEF1001):
PCI device 0000:15:00.0 rev 00 IOMMU group 41 physical slot 3-1
DMA bridge bar 0 memory size 0x120000
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
H2C 1 1 1 64
C2H 0 1 1 64
C2H 1 1 1 64
Design AS02MC04_dma_stream_crc64:
PCI device 0000:2d:00.0 rev 00 IOMMU group 25 physical slot 5-2
DMA bridge bar 2 AXI Stream
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
H2C 1 1 1 64
H2C 2 1 1 64
H2C 3 1 1 64
C2H 0 1 1 64
C2H 1 1 1 64
C2H 2 1 1 64
C2H 3 1 1 64
User access build timestamp : 14332B0F - 02/08/2025 18:44:15
Quad SPI registers at bar 0 offset 0x0
SYSMON registers at bar 0 offset 0x1000
Design Nitefury Project-0 version 0x2:
PCI device 0000:37:00.0 rev 00 IOMMU group 86 physical slot 6-1
DMA bridge bar 2 memory size 0x40000000
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
C2H 0 1 1 64
Quad SPI registers at bar 0 offset 0x10000
XADC registers at bar 0 offset 0x3000
The results:
$ xilinx_dma_bridge_for_pcie/crc64_stream_latency -t
Opening device 0000:15:00.0 (10ee:7024) with IOMMU group 41
Enabled bus master for 0000:15:00.0
Opening device 0000:2d:00.0 (10ee:9038) with IOMMU group 25
Enabled bus master for 0000:2d:00.0
Warning: Device device 0000:2d:00.0 (10ee:9038) has reduced bandwidth
Max width x8 speed 8 GT/s. Negotiated width x4 speed 8 GT/s
Opening device 0000:37:00.0 (10ee:7011) with IOMMU group 86
Enabled bus master for 0000:37:00.0
Testing design AS02MC04_dma_stream_crc64 using C2H 0 -> H2C 0
Current temperature 41.3C min 39.3C max 44.3C
32 len bytes latencies (us): 2.642 (50') 2.780 (75') 3.258 (99') 18.868 (99.999')
64 len bytes latencies (us): 2.619 (50') 2.624 (75') 2.645 (99') 13.076 (99.999')
128 len bytes latencies (us): 2.653 (50') 2.662 (75') 2.683 (99') 18.028 (99.999')
256 len bytes latencies (us): 2.724 (50') 2.733 (75') 2.754 (99') 11.898 (99.999')
512 len bytes latencies (us): 2.832 (50') 2.840 (75') 2.865 (99') 13.051 (99.999')
1024 len bytes latencies (us): 2.974 (50') 2.981 (75') 3.008 (99') 18.005 (99.999')
2048 len bytes latencies (us): 3.263 (50') 3.276 (75') 3.310 (99') 17.748 (99.999')
4096 len bytes latencies (us): 3.861 (50') 3.872 (75') 3.905 (99') 19.126 (99.999')
8192 len bytes latencies (us): 4.986 (50') 5.000 (75') 5.034 (99') 20.762 (99.999')
16384 len bytes latencies (us): 7.297 (50') 7.310 (75') 7.339 (99') 23.028 (99.999')
32768 len bytes latencies (us): 12.014 (50') 12.043 (75') 12.387 (99') 25.745 (99.999')
65536 len bytes latencies (us): 21.370 (50') 21.419 (75') 21.729 (99') 38.491 (99.999')
131072 len bytes latencies (us): 40.062 (50') 40.090 (75') 40.548 (99') 55.257 (99.999')
262144 len bytes latencies (us): 77.365 (50') 77.421 (75') 77.838 (99') 92.264 (99.999')
524288 len bytes latencies (us): 152.354 (50') 152.530 (75') 152.675 (99') 166.228 (99.999')
1048576 len bytes latencies (us): 301.333 (50') 301.380 (75') 301.905 (99') 315.720 (99.999')
Current temperature 41.3C min 39.3C max 45.3C
When reboot the link goes down and doesn't come back up.
This doesn't enumerate, neither after loading over JTAG nor after a subsequent reboot.
Tried changing the IOSTANDARD to LVCMOS33, but didn't change the result:
set_property IOSTANDARD LVCMOS33 [get_ports PCI_PERSTN]
set_property PACKAGE_PIN A9 [get_ports {PCI_PERSTN}]Tried changing the reset pin to T19 which was the initial pin used in https://github.com/TiferKing/as02mc04_hack/blob/main/as02mc04/1.0/part0_pins.xml, but didn't change the result:
set_property IOSTANDARD LVCMOS18 [get_ports PCI_PERSTN]
set_property PACKAGE_PIN T19 [get_ports {PCI_PERSTN}]This enumerates after loading over JTAG, as x4 width on physical slot 5-2.
If reboot with the design loaded, the link goes down and doesn't come up at reboot.
After downgrading from v2025.1 to v2024.2 to enable the JTAG debugger in XDMA and avoid the issue in 2.3. Investigating JTAG debugger with the JTAG debugger not working, this still enumerated as a x4 width on physical slot 5-2:
$ identify_pcie_fpga_design/display_identified_pcie_fpga_designs
Opening device 0000:2d:00.0 (10ee:9038) with IOMMU group 26
Enabled bus master for 0000:2d:00.0
Warning: Device device 0000:2d:00.0 (10ee:9038) has reduced bandwidth
Max width x8 speed 8 GT/s. Negotiated width x4 speed 8 GT/s
Opening device 0000:37:00.0 (10ee:7011) with IOMMU group 86
Enabled bus master for 0000:37:00.0
Design AS02MC04_enum:
PCI device 0000:2d:00.0 rev 01 IOMMU group 26 physical slot 5-2
DMA bridge bar 1 memory size 0x1000
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
C2H 0 1 1 64
User access build timestamp : FC334B0A - 31/08/2025 20:44:10
Design Nitefury Project-0 version 0x2:
PCI device 0000:37:00.0 rev 00 IOMMU group 86 physical slot 6-1
DMA bridge bar 2 memory size 0x40000000
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
C2H 0 1 1 64
Quad SPI registers at bar 0 offset 0x10000
XADC registers at bar 0 offset 0x3000
The test_rd.tcl script ran:
source -notrace AS02MC04_enum/AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/AS02MC04_enum_xdma_0_0_pcie4_ip/pcie_debugger/test_rd.tcl
Identified PCIe debugger with hw_axi_1
INFO: [Labtoolstcl 44-481] READ DATA is: 00000901
INFO: [Labtoolstcl 44-481] READ DATA is: 00000001
INFO: [Labtoolstcl 44-481] READ DATA is: 00000009
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
INFO: [Labtoolstcl 44-481] READ DATA is: 00001001
INFO: [Labtoolstcl 44-481] READ DATA is: 0000abcd
INFO: [Labtoolstcl 44-481] READ DATA is: 00000000
phy_lane : 8
width : 04
speed : 03
draw_rxdet.tcl indicated a receiver was detected in all 8 lanes:
$ wish AS02MC04_enum/AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/AS02MC04_enum_xdma_0_0_pcie4_ip/pcie_debugger/draw_rxdet.tcl
phy_lane : 8
width : 4
speed : 03
count = 1
i = 0
count = 2
i = 0
line1 = 13
Receiver detected in lane 0
count = 3
i = 0
Receiver detected in lane 0
count = 4
i = 0
Receiver detected in lane 0
count = 5
i = 4
count = 6
i = 4
line1 = 13
Receiver detected in lane 1
count = 7
i = 4
Receiver detected in lane 1
count = 8
i = 4
Receiver detected in lane 1
count = 9
i = 8
count = 10
i = 8
line1 = 13
Receiver detected in lane 2
count = 11
i = 8
Receiver detected in lane 2
count = 12
i = 8
Receiver detected in lane 2
count = 13
i = 12
count = 14
i = 12
line1 = 13
Receiver detected in lane 3
count = 15
i = 12
Receiver detected in lane 3
count = 16
i = 12
Receiver detected in lane 3
count = 17
i = 16
count = 18
i = 16
line1 = 13
Receiver detected in lane 4
count = 19
i = 16
Receiver detected in lane 4
count = 20
i = 16
Receiver detected in lane 4
count = 21
i = 20
count = 22
i = 20
line1 = 13
Receiver detected in lane 5
count = 23
i = 20
Receiver detected in lane 5
count = 24
i = 20
Receiver detected in lane 5
count = 25
i = 24
count = 26
i = 24
line1 = 13
Receiver detected in lane 6
count = 27
i = 24
Receiver detected in lane 6
count = 28
i = 24
Receiver detected in lane 6
count = 29
i = 28
count = 30
i = 28
line1 = 13
Receiver detected in lane 7
count = 31
i = 28
Receiver detected in lane 7
count = 32
i = 28
Receiver detected in lane 7
Output from draw_reset.tcl:
Output from draw_ltssm.tcl:
There looks to be a enable_lane_reversal configuration property which can be changed for the XDMA IP:
list_property [get_ips *xdma*] *lane*
CONFIG.enable_lane_reversal CONFIG.lane_order
get_property CONFIG.lane_order [get_ips AS02MC04_enum_xdma_0_0]
Bottom
get_property CONFIG.enable_lane_reversal [get_ips AS02MC04_enum_xdma_0_0]
false
Searching for LANE_REVERSAL in the generated IP source files finds:
- AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/source/AS02MC04_enum_xdma_0_0_pcie4_ip_pipe.v :
parameter PL_DISABLE_LANE_REVERSAL="FALSE"forPCIE40E4 - AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/source/AS02MC04_enum_xdma_0_0_pcie4_ip_pcie4_uscale_core_top.v :
parameter PL_DISABLE_LANE_REVERSAL="FALSE"forAS02MC04_enum_xdma_0_0_pcie4_ip_pipe - AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/synth/AS02MC04_enum_xdma_0_0_pcie4_ip.v :
PL_DISABLE_LANE_REVERSAL("TRUE")forAS02MC04_enum_xdma_0_0_pcie4_ip_pcie4_uscale_core_top
Lane Reversal in UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213) has@
Important: By default EndPoint configuration has Lane Reversal Support disabled through the attribute
DISABLE_LANE_REVERSAL. Lane Reversal as an EndPoint must not be enabled if the Link Partner has Lane Reversal capability.
It isn't clear why different IPs have PL_DISABLE_LANE_REVERSAL as TRUE or FALSE, and what the impact of that is.
In the Tcl Console set CONFIG.enable_lane_reversal to true:
set_property CONFIG.enable_lane_reversal true [get_ips AS02MC04_enum_xdma_0_0]
INFO: [Device 21-403] Loading part xcku3p-ffvb676-1-e
xit::create_sub_core: Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 9479.262 ; gain = 1060.719 ; free physical = 9024 ; free virtual = 83374
xit::create_sub_core: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 9479.262 ; gain = 0.000 ; free physical = 9068 ; free virtual = 83420
true
Which read back with the change:
get_property CONFIG.enable_lane_reversal [get_ips AS02MC04_enum_xdma_0_0]
true
Tried building building the FPGA with this parameter change. However:
- The AS02MC04_enum.srcs/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/AS02MC04_enum_xdma_0_0.xci showed the change to the
enable_lane_reversalparameter. - The following generated files showed no change:
- AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/synth/AS02MC04_enum_xdma_0_0_pcie4_ip.v still had
.PL_DISABLE_LANE_REVERSAL("TRUE") - AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/source/AS02MC04_enum_xdma_0_0_pcie4_ip_pipe.v still had
parameter PL_DISABLE_LANE_REVERSAL="FALSE". - AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/source/AS02MC04_enum_xdma_0_0_pcie4_ip_pcie4_uscale_core_top.v still had
parameter PL_DISABLE_LANE_REVERSAL="FALSE",
- AS02MC04_enum.gen/sources_1/bd/AS02MC04_enum/ip/AS02MC04_enum_xdma_0_0/ip_0/synth/AS02MC04_enum_xdma_0_0_pcie4_ip.v still had
- Vivado 2024.2 and 2025.2 behaved in the same way (2025.2 has a later version of the XMDA IP)
- The FGPA built this this parameter change using Vivado 2025.2 had the same enumeration issue as that without the parameter change.
/opt/Xilinx/Vivado/2024.2/data/ip/xilinx/xdma_v4_1/xgui/xdma_v4_1.tcl has the following which enables the enable_lane_reversal parameter on the GUI for only some devices:
proc update_gui_for_PARAM_VALUE.enable_lane_reversal {PARAM_VALUE.enable_lane_reversal PROJECT_PARAM.ARCHITECTURE PROJECT_PARAM.DEVICE IPINST} {
set c_xfamily_gen2 [string toupper ${PROJECT_PARAM.ARCHITECTURE}]
set device [string toupper ${PROJECT_PARAM.DEVICE}]
if {$device == "XC7VX485T" || $device == "XC7V585T" || $device == "XC7V2000T" || $device == "XQ7V585T" || $device == "XQ7VX485T" || $c_xfamily_gen2 == "KINTEX7" || $c_xfamily_gen2 == "QKINTEX7" || $c_xfamily_gen2 == "KINTEX7L" || $c_xfamily_gen2 == "QKINTEX7L" || $c_xfamily_gen2 == "ARTIX7" || $c_xfamily_gen2 == "AARTIX7" || $c_xfamily_gen2 == "QARTIX7" || $c_xfamily_gen2 == "ARTIX7L" || $c_xfamily_gen2 == "ZYNQ" || $c_xfamily_gen2 == "AZYNQ" || $c_xfamily_gen2 == "QZYNQ"} {
set_property visible true [ipgui::get_guiparamspec enable_lane_reversal -of $IPINST ]
} else {
set_property visible false [ipgui::get_guiparamspec enable_lane_reversal -of $IPINST ]
}
}Where a Kintex UltraScale+ device isn't one in which the parameter is enabled on the GUI, which would explain why changing the parameter via TCL had no effect.
This enumerated after loading over JTAG, as x4 width on physical slot 5-2.
If reboot with the design loaded, the link goes down and then back up about one second later.
This enumerated after loading over JTAG, as x4 width on physical slot 5-2.
If reboot with the design loaded, the link goes down and then back up about one second later.
With the previous gen3_x4_quad224_reversed_lane_order loaded, loaded gen3_x4_quad225_example_order and the link went down and didn't come back up.
After a reboot the link came up as x4 width with no physical slot set.
With the previous gen3_x4_quad225_example_order, loaded gen3_x4_quad225_reversed_lane_order and the link went down and the PC rebooted itself a short time later. Following the reboot the link came up as x4 width with no physical slot set.
Rebooting to look at the BIOS event log showed:
PCIe Surprise Link Down error detected on Slot 0. B:2C D:1 F:0
The error is on the PCIe Root Port to which gen3_x4_quad225_reversed_lane_order was using.
As per gen3_x8_reversed_lane_order, but with a ILA connected to the PCIe pipe debug. In the same way as gen3_x8_reversed_lane_order:
- This enumerates after loading over JTAG, as x4 width on physical slot 5-2.
- If reboot with the design loaded, the link goes down and doesn't come up at reboot.
By adding the ILA to monitor the PCIe pipe debug had hoped to monitor what happened on lanes 4..7 during the enumeration which failed to get to using 8 lanes. However, since can only get the PCIe enumeration to work when load over JTAG while Linux is booted, have failed to capture any data on Rx lanes 4..7.
After has loaded and therefore enumerates can only capture data on Rx lanes 4..7.
From Understanding PCIe Link Training the Link configuration which determines What width and lane ordering to use only happens at the initial gen1 speed.
Since the configuration memory had a design which didn't enumerate at power up, could have been causing the BIOS to set endup with a x4x4 bifurcation. Therefore, investigate erasing the configuration memory.
With the Vivado Hardware Manager erased the configuration memory with Address Range at the default of Configuration File Only. The Vivado Tcl Console report the erease and blank check was successful:
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcku3p_0] 0]]
Mfg ID : 20 Memory Type : bb Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
Performing Erase Operation...
Erase Operation successful.
Performing Blank Check Operation...
Blank Check Operation successful. The part is blank.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:03 ; elapsed = 00:01:32 . Memory (MB): peak = 10391.516 ; gain = 0.000 ; free physical = 21232 ; free virtual = 29491
endgroup
However, after loading AS02MC04_dma_stream_crc64 over JTAG quad_spi_flasher still found a bitstream in flash:
Displaying information for SPI flash using AS02MC04_dma_stream_crc64 design in PCI device 0000:2d:00.0 IOMMU group 25
Initial device identification incorrect - ignoring due to Quad SPI core not outputting initial clock cycles
FIFO depth=256
Flash device : Micron N25Q256A
Manufacturer ID=0x20 Memory Interface Type=0xbb Density=0x19
Flash Size Bytes=33554432 Page Size Bytes=256 Num Address Bytes=4
Successfully parsed bitstream of length 32212444 bytes with 466 configuration packets
Read 32243712 bytes from SPI flash starting at address 0
Sync word at byte index 0x1001050
Type 1 packet opcode NOP
Type 1 packet opcode write register BSPI words 0000066C
Type 1 packet opcode write register CMD command BSPI_READ
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register TIMER words 00000000
Type 1 packet opcode write register WBSTAR words 00000000
Type 1 packet opcode write register CMD command NULL
Type 1 packet opcode NOP
Type 1 packet opcode write register CMD command RCRC
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register FAR words 00000000
Type 1 packet opcode write register RBCRC_SW words 00000000
Type 1 packet opcode write register COR0 words 383A3FE5
Type 1 packet opcode write register COR1 words 00400000
Type 1 packet opcode write register IDCODE KU3P
Type 1 packet opcode write register CMD command FALL_EDGE
Type 1 packet opcode write register CMD command SWITCH
Type 1 packet opcode NOP
Type 1 packet opcode write register MASK words 00000001
Type 1 packet opcode write register CTL0 words 00000101
Type 1 packet opcode write register MASK words 00000000
Type 1 packet opcode write register CTL1 words 00000000
Type 1 packet opcode NOP (8 consecutive)
Configuration data writes consisting of:
1 NOPs
1 FAR writes
1 WCFG commands
1 FDRI writes with a total of 0 words
1 Type 2 packets with a total of 3857268 words
Type 1 packet opcode write register CRC words 6E1E7B1E
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register CMD command GRESTORE
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register CMD command DGHIGH_LFRM
Type 1 packet opcode NOP (20 consecutive)
Type 1 packet opcode write register CMD command START
Type 1 packet opcode NOP
Type 1 packet opcode write register FAR words 07FC0000
Type 1 packet opcode write register MASK words 00000101
Type 1 packet opcode write register CTL0 words 00000101
Type 1 packet opcode write register CRC words DD03E29D
Type 1 packet opcode NOP (2 consecutive)
Type 1 packet opcode write register CMD command DESYNC
Type 1 packet opcode NOP (393 consecutive)
The Sync word being found at byte offset 0x1001050, which is just over half way through the QSPI address range suggests a fallback image.
boot_hw_device.sh indicated the FPGA could still boot from the configuration memory:
source /home/mr_halfword/fpga_sio/multiple_boards/boot_hw_device.tcl -notrace
Booting xcku3p_0
INFO: [Labtoolstcl 44-664] Will wait up to 180 seconds for booting to complete.
INFO: [Labtools 27-32] Done pin status: HIGH
boot_hw_device: Time (s): cpu = 00:00:00.05 ; elapsed = 00:01:08 . Memory (MB): peak = 2012.297 ; gain = 0.000 ; free physical = 20120 ; free virtual = 28795
Initially was confused while when selected only an Erase operation, Vivado reported an error if no configuration file was specified, but subsequently realised that the Address Range of Configuration File Only is what required the configuration file to be specified before the partial erase could be performed.
While found a bitstream with a Sync word offset at both offset 0x50 and 0x1001050 they both had:
- WBSTAR (Warm Boot Start Address Register) is zero
- No IPROG cmmand
So, can't see any automatic fallback if one bitstream fails to load.
Performed another erase in the Hardware Manager, but this time the Address Range was set to Erase Configuration Memory Device.
The Vivado Tcl Console reported success, with a longer elapsed time than the partial erase:
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xcku3p_0] 0]]
Mfg ID : 20 Memory Type : bb Memory Capacity : 19 Device ID 1 : 0 Device ID 2 : 0
Performing Erase Operation...
Erase Operation successful.
Performing Blank Check Operation...
Blank Check Operation successful. The part is blank.
INFO: [Labtoolstcl 44-377] Flash programming completed successfully
program_hw_cfgmem: Time (s): cpu = 00:00:18 ; elapsed = 00:08:35 . Memory (MB): peak = 10391.516 ; gain = 0.000 ; free physical = 20470 ; free virtual = 29164
After loading AS02MC04_dma_stream_crc64 over JTAG quad_spi_flasher can no longer find a bitstream:
isplaying information for SPI flash using AS02MC04_dma_stream_crc64 design in PCI device 0000:2d:00.0 IOMMU group 25
Initial device identification incorrect - ignoring due to Quad SPI core not outputting initial clock cycles
FIFO depth=256
Flash device : Micron N25Q256A
Manufacturer ID=0x20 Memory Interface Type=0xbb Density=0x19
Flash Size Bytes=33554432 Page Size Bytes=256 Num Address Bytes=4
Error parsing bitstream: No Sync word found
Read 33554432 bytes from SPI flash starting at address 0
And boot_hw_device.sh now reports a failure to boot from configuration memory:
source /home/mr_halfword/fpga_sio/multiple_boards/boot_hw_device.tcl -notrace
Booting xcku3p_0
INFO: [Labtoolstcl 44-664] Will wait up to 180 seconds for booting to complete.
ERROR: [Labtools 27-2254] Booting from configuration memory device unsuccessful.
boot_hw_device: Time (s): cpu = 00:00:00.12 ; elapsed = 00:03:01 . Memory (MB): peak = 2012.297 ; gain = 0.000 ; free physical = 19919 ; free virtual = 28718
ERROR: [Common 17-39] 'boot_hw_device' failed due to earlier errors
Powered up with the configuration flash erased. There were two x4 root ports for slot 5:
$ dump_info/dump_pci_info_pciutils 8086:2030 8086:2031
domain=0000 bus=2c dev=00 func=00 rev=04
vendor_id=8086 (Intel Corporation) device_id=2030 (Sky Lake-E PCI Express Root Port A)
iommu_group=74
driver=pcieport
physical_slot=5
control: I/O+ Mem+ BusMaster+ ParErr- SERR- DisINTx+
status: INTx- <ParErr- >TAbort- <TAbort- <MAbort- >SERR- DetParErr-
Capabilities: [40] Bridge subsystem vendor/device ID
Capabilities: [60] Message Signaled Interrupts
Capabilities: [90] PCI Express v2 Root Port, MSI 0
Link capabilities: Max speed 8 GT/s Max width x4
Negotiated link status: Current speed 2.5 GT/s Width x0
Link capabilities2: Supported link speeds 2.5 GT/s 5.0 GT/s 8.0 GT/s
DevCap: MaxPayload 256 bytes PhantFunc 0 Latency L0s Maximum of 64 ns L1 Maximum of 1 μs
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop-
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port # 9 ASPM not supported
L0s Exit Latency 256 ns to less than 512 ns
L1 Exit Latency 8 μs to less than 16 μs
ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- ABWMgmt-
LnkSta: TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise-
Slot #5 PowerLimit 0.000W Interlock- NoCompl-
Capabilities: [e0] Power Management
<<snip>>
domain=0000 bus=2c dev=01 func=00 rev=04
vendor_id=8086 (Intel Corporation) device_id=2031 (Sky Lake-E PCI Express Root Port B)
iommu_group=75
driver=pcieport
physical_slot=5-1
control: I/O+ Mem+ BusMaster+ ParErr- SERR- DisINTx+
status: INTx- <ParErr- >TAbort- <TAbort- <MAbort- >SERR- DetParErr-
Capabilities: [40] Bridge subsystem vendor/device ID
Capabilities: [60] Message Signaled Interrupts
Capabilities: [90] PCI Express v2 Root Port, MSI 0
Link capabilities: Max speed 8 GT/s Max width x4
Negotiated link status: Current speed 2.5 GT/s Width x0
Link capabilities2: Supported link speeds 2.5 GT/s 5.0 GT/s 8.0 GT/s
DevCap: MaxPayload 256 bytes PhantFunc 0 Latency L0s Maximum of 64 ns L1 Maximum of 1 μs
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop-
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port # 10 ASPM not supported
L0s Exit Latency 256 ns to less than 512 ns
L1 Exit Latency 8 μs to less than 16 μs
ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled RCB 64 bytes Disabled+ CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- ABWMgmt-
LnkSta: TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #5 PowerLimit 0.000W Interlock- NoCompl-
Capabilities: [e0] Power Management
In the BIOS changed the slot 5 bifurcation from Auto to x8. On a power cycle that still resulted in slot 5 having two x4 slots. Therefore, changed the slot 5 bifurcation back to Auto.
This fails to enumerate, either after loading over JTAG or rebooting.
This enumerated after loading over JTAG, as x4 width on physical slot 5-2.
If reboot with the design loaded, the link goes down and doesn't come up at reboot.
This enumerated after loading over JTAG, as x4 width on physical slot 5-2. Found that the load over JTAG when the PC has been powered on fails to enumerate, but the second and subsequent to allow to enumerate (repeated on two power up attempts).
If reboot with the design loaded, the link goes down and doesn't come up at reboot.
With the QDMA IP, under Debug and Additional Options there is a Enable Lane Reversal checkbox. For this design left at the default of disabled.
Compared to the AS02MC04_qdma_enum/gen3_x8_reversed_lane_order, set the Enable Lane Reversal checkbox in the QDMA configuration. Searched for LANE_REVERSAL in the source files, and compared the rssults between AS02MC04_qdma_enum/gen3_x8_reversed_lane_order and AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled:
$ git diff ~/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/LANE_REVERSAL.txt ~/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/LANE_REVERSAL.txt | cat
diff --git a/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/LANE_REVERSAL.txt b/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/LANE_REVERSAL.txt
index 71a2c4c..32ec855 100644
--- a/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/LANE_REVERSAL.txt
+++ b/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/LANE_REVERSAL.txt
@@ -1,31 +1,31 @@
Found usages (20 usages)
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/ip_0/source/AS02MC04_qdma_enum_qdma_0_0_pcie4_ip_pipe.v (3 usages)
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/ip_0/source/AS02MC04_qdma_enum_qdma_0_0_pcie4_ip_pipe.v (3 usages)
(180, 37) , parameter PL_DISABLE_LANE_REVERSAL="FALSE"
(1692, 17) ,.PL_DISABLE_LANE_REVERSAL(PL_DISABLE_LANE_REVERSAL)
(1692, 42) ,.PL_DISABLE_LANE_REVERSAL(PL_DISABLE_LANE_REVERSAL)
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/ip_0/source/AS02MC04_qdma_enum_qdma_0_0_pcie4_ip_pcie4_uscale_core_top.v (5 usages)
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/ip_0/source/AS02MC04_qdma_enum_qdma_0_0_pcie4_ip_pcie4_uscale_core_top.v (5 usages)
(176, 34) parameter PL_DISABLE_LANE_REVERSAL="FALSE",
(2280, 17) ,.PL_DISABLE_LANE_REVERSAL(PL_DISABLE_LANE_REVERSAL)
(2280, 42) ,.PL_DISABLE_LANE_REVERSAL(PL_DISABLE_LANE_REVERSAL)
(3742, 17) ,.PL_DISABLE_LANE_REVERSAL(PL_DISABLE_LANE_REVERSAL)
(3742, 42) ,.PL_DISABLE_LANE_REVERSAL(PL_DISABLE_LANE_REVERSAL)
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/ip_0/sim/AS02MC04_qdma_enum_qdma_0_0_pcie4_ip.v (1 usage)
-(789, 17) .PL_DISABLE_LANE_REVERSAL("TRUE"),
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/ip_0/synth/AS02MC04_qdma_enum_qdma_0_0_pcie4_ip.v (2 usages)
-(71, 421) BAR5_APERTURE_SIZE=0x00,PF3_SRIOV_BAR5_CONTROL=0x0,PF3_SRIOV_CAP_INITIAL_VF=0x0000,PF3_SRIOV_CAP_NEXTPTR=0x000,PF3_SRIOV_CAP_TOTAL_VF=0x0000,PF3_SRIOV_CAP_VER=0x1,PF3_SRIOV_FIRST_VF_OFFSET=0x0000,PF3_SRIOV_FUNC_DEP_LINK=0x0003,PF3_SRIOV_SUPPORTED_PAGE_SIZE=0x00000553,PF3_SRIOV_VF_DEVICE_ID=0x0000,PF3_SUBSYSTEM_ID=0x0007,PF3_TPHR_CAP_NEXTPTR=0x000,PL_UPSTREAM_FACING=TRUE,AXISTEN_IF_LEGACY_MODE_ENABLE=FALSE,PL_DISABLE_LANE_REVERSAL=TRUE,PF0_MSI_CAP_PERVECMASKCAP=FALSE,PF1_MSI_CAP_PERVECMASKCAP=FAL\
-(818, 17) .PL_DISABLE_LANE_REVERSAL("TRUE"),
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/AS02MC04_qdma_enum_qdma_0_0hdl/verilog/AS02MC04_qdma_enum_qdma_0_0_core_top.sv (1 usage)
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/ip_0/sim/AS02MC04_qdma_enum_qdma_0_0_pcie4_ip.v (1 usage)
+(789, 17) .PL_DISABLE_LANE_REVERSAL("FALSE"),
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/ip_0/synth/AS02MC04_qdma_enum_qdma_0_0_pcie4_ip.v (2 usages)
+(71, 421) BAR5_APERTURE_SIZE=0x00,PF3_SRIOV_BAR5_CONTROL=0x0,PF3_SRIOV_CAP_INITIAL_VF=0x0000,PF3_SRIOV_CAP_NEXTPTR=0x000,PF3_SRIOV_CAP_TOTAL_VF=0x0000,PF3_SRIOV_CAP_VER=0x1,PF3_SRIOV_FIRST_VF_OFFSET=0x0000,PF3_SRIOV_FUNC_DEP_LINK=0x0003,PF3_SRIOV_SUPPORTED_PAGE_SIZE=0x00000553,PF3_SRIOV_VF_DEVICE_ID=0x0000,PF3_SUBSYSTEM_ID=0x0007,PF3_TPHR_CAP_NEXTPTR=0x000,PL_UPSTREAM_FACING=TRUE,AXISTEN_IF_LEGACY_MODE_ENABLE=FALSE,PL_DISABLE_LANE_REVERSAL=FALSE,PF0_MSI_CAP_PERVECMASKCAP=FALSE,PF1_MSI_CAP_PERVECMASKCAP=FA\
+(818, 17) .PL_DISABLE_LANE_REVERSAL("FALSE"),
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/AS02MC04_qdma_enum_qdma_0_0hdl/verilog/AS02MC04_qdma_enum_qdma_0_0_core_top.sv (1 usage)
(750, 24) parameter PL_DISABLE_LANE_REVERSAL = "FALSE",
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/sim/AS02MC04_qdma_enum_qdma_0_0.sv (1 usage)
-(842, 17) .PL_DISABLE_LANE_REVERSAL("TRUE"),
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/AS02MC04_qdma_enum_qdma_0_0_stub.v (1 usage)
-(17, 11794) (* CHECK_LICENSE_TYPE = "AS02MC04_qdma_enum_qdma_0_0,AS02MC04_qdma_enum_qdma_0_0_core_top,{}" *) (* CORE_GENERATION_INFO = "AS02MC04_qdma_enum_qdma_0_0,AS02MC04_qdma_enum_qdma_0_0_core_top,{x_ipProduct=Vivado 2025.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=qdma,x_ipVersion=5.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,PL_UPSTREAM_FACING=true,TL_LEGACY_MODE_ENABLE=false,PCIE_BLK_LOCN=0,PL_LINK_CAP_MAX_LINK_WIDTH=8,PL_LINK_CAP_MAX_LINK_SPEED=4,REF_CLK_FREQ=0,DRP_CLK_SEL=0,FREE_RUN_FREQ=0,AXI_ADDR_WIDTH=64,AXI_DATA_WIDTH=256,CORE_CLK_FREQ=1,PLL_TYPE=2,USER_CLK_FREQ=2,SILICON_REV=Pre-Production,PIPE_SIM=FALSE,EGW_IS_PARENT_IP=1,EXT_CH_GT_DRP=false,PCIE3_DRP=false,DEDICATE_PERST=true,SYS_RESET_POLARITY=0,MCAP_ENABLEMENT=NONE,EXT_STARTUP_PRIMITIVE=false,RBAR_ENABLE=FALSE,PF0_VENDOR_ID=0x10EE,PF0_DEVICE_ID=0x9038,PF0_REVISION_ID=0x00,PF0_SUBSYSTEM_VENDOR_ID=0x0002,PF0_SUBSYSTEM_ID=0x002A,PF1_VENDOR_ID=0x10EE,PF1_DEVICE_ID=0x913F,PF1_REVISION_ID=0x00,PF1_SUBSYSTEM_VENDOR_ID=0x0002,PF1_SUBSYSTEM_ID=0x0007,PF2_VENDOR_ID=0x10EE,PF2_DEVICE_ID=0x9238,PF2_REVISION_ID=0x00,PF2_SUBSYSTEM_VENDOR_ID=0x10EE,PF2_SUBSYSTEM_ID=0x0007,PF3_VENDOR_ID=0x10EE,PF3_DEVICE_ID=0x9338,PF3_REVISION_ID=0x00,PF3_SUBSYSTEM_VENDOR_ID=0x10EE,PF3_SUBSYSTEM_ID=0x0007,AXILITE_MASTER_APERTURE_SIZE=0x0D,AXILITE_MASTER_CONTROL=0x4,XDMA_APERTURE_SIZE=0x0D,XDMA_CONTROL=0x4,AXIST_BYPASS_APERTURE_SIZE=0x00,AXIST_BYPASS_CONTROL=0x0,PF0_INTERRUPT_PIN=0x1,PF1_INTERRUPT_PIN=0x1,PF2_INTERRUPT_PIN=0x1,PF3_INTERRUPT_PIN=0x1,PF0_MSI_CAP_MULTIMSGCAP=0,C_COMP_TIMEOUT=1,C_TIMEOUT0_SEL=0xE,C_TIMEOUT1_SEL=0xF,C_TIMEOUT_MULT=0x3,C_OLD_BRIDGE_TIMEOUT=0,SHARED_LOGIC=1,SHARED_LOGIC_CLK=false,SHARED_LOGIC_BOTH=false,SHARED_LOGIC_GTC=false,EN_TRANSCEIVER_STATUS_PORTS=FALSE,IS_BOARD_PROJECT=0,EN_GT_SELECTION=FALSE,SELECT_QUAD=GTY_Quad_227,ULTRASCALE=FALSE,ULTRASCALE_PLUS=TRUE,VERSAL=FALSE,V7_GEN3=FALSE,MSI_ENABLED=FALSE,RP_MSI_ENABLED=TRUE,DEV_PORT_TYPE=0,XDMA_AXI_INTF_MM=1,XDMA_PCIE_64BIT_EN=false,XDMA_AXILITE_MASTER=TRUE,XDMA_AXIST_BYPASS=FALSE,XDMA_RNUM_CHNL=4,XDMA_WNUM_CHNL=4,XDMA_AXILITE_SLAVE=FALSE,CSR_AXILITE_SLAVE=FALSE,XDMA_NUM_USR_IRQ=16,XDMA_RNUM_RIDS=32,XDMA_WNUM_RIDS=32,C_M_AXI_ID_WIDTH=4,C_AXIBAR_NUM=1,C_FAMILY=kintexuplus,XDMA_NUM_PCIE_TAG=256,EN_AXI_MASTER_IF=FALSE,XDMA_DSC_BYPASS=FALSE,C_METERING_ON=1,RX_DETECT=0,C_ATS_ENABLE=FALSE,C_ATS_CAP_NEXTPTR=0x000,C_PR_CAP_NEXTPTR=0x000,C_PRI_ENABLE=FALSE,DSC_BYPASS_RD=0,DSC_BYPASS_WR=0,DSC_BYPASS_RD_OUT=0,DSC_BYPASS_WR_OUT=0,XDMA_STS_PORTS=FALSE,MSIX_ENABLED=TRUE,CFG_MGMT_IF=TRUE,RQ_SEQ_NUM_IGNORE=0,CFG_EXT_IF=FALSE,LEGACY_CFG_EXT_IF=FALSE,C_PARITY_PROP=0,EN_DEBUG_PORTS=FALSE,VU9P_BOARD=FALSE,ENABLE_JTAG_DBG=TRUE,ENABLE_IBERT=FALSE,MM_SLAVE_EN=0,DMA_EN=1,C_AXIBAR_0=0x0000000000000000,C_AXIBAR_1=0x0000000000000000,C_AXIBAR_2=0x0000000000000000,C_AXIBAR_3=0x0000000000000000,C_AXIBAR_4=0x0000000000000000,C_AXIBAR_5=0x0000000000000000,C_AXIBAR_HIGHADDR_0=0x0000000000000000,C_AXIBAR_HIGHADDR_1=0x0000000000000000,C_AXIBAR_HIGHADDR_2=0x0000000000000000,C_AXIBAR_HIGHADDR_3=0x0000000000000000,C_AXIBAR_HIGHADDR_4=0x0000000000000000,C_AXIBAR_HIGHADDR_5=0x0000000000000000,C_AXIBAR2PCIEBAR_0=0x0000000000000000,C_AXIBAR2PCIEBAR_1=0x0000000000000000,C_AXIBAR2PCIEBAR_2=0x0000000000000000,C_AXIBAR2PCIEBAR_3=0x0000000000000000,C_AXIBAR2PCIEBAR_4=0x0000000000000000,C_AXIBAR2PCIEBAR_5=0x0000000000000000,MINIMAL_DMA_EN=FALSE,EN_AXI_SLAVE_IF=TRUE,C_INCLUDE_BAROFFSET_REG=1,C_BASEADDR=0x00001000,C_HIGHADDR=0x00001FFF,C_S_AXI_ID_WIDTH=4,C_S_AXI_NUM_READ=32,C_M_AXI_NUM_READ=32,C_S_AXI_NUM_WRITE=32,C_M_AXI_NUM_WRITE=16,MSIX_IMPL_EXT=TRUE,AXI_ACLK_LOOPBACK=FALSE,PCIEBAR_NUM=6,PF0_BAR0_APERTURE_SIZE=0x0B,PF0_BAR1_APERTURE_SIZE=0x00,PF0_BAR2_APERTURE_SIZE=0x05,PF0_BAR3_APERTURE_SIZE=0x00,PF0_BAR4_APERTURE_SIZE=0x00,PF0_BAR5_APERTURE_SIZE=0x00,PF0_BAR6_APERTURE_SIZE=0x00,PF0_BAR0_CONTROL=0x6,PF0_BAR1_CONTROL=0x0,PF0_BAR2_CONTROL=0x6,PF0_BAR3_CONTROL=0x0,PF0_BAR4_CONTROL=0x0,PF0_BAR5_CONTROL=0x0,PF0_BAR6_CONTROL=0x0,PF0_SRIOV_BAR0_CONTROL=0x7,PF0_SRIOV_BAR1_CONTROL=0x0,PF0_SRIOV_BAR2_CONTROL=0x7,PF0_SRIOV_BAR3_CONTROL=0x0,PF0_SRIOV_BAR4_CONTROL=0x0,PF0_SRIOV_BAR5_CONTROL=0x0,PF0_ADDR_MASK=0x0000000000000FFF,PF1_ADDR_MASK=0x0000000000000FFF,PF2_ADDR_MASK=0x0000000000000FFF,PF3_ADDR_MASK=0x0000000000000FFF,PF0_VF_ADDR_MASK=0x0000000000000FFF,PF1_VF_ADDR_MASK=0x0000000000000FFF,PF2_VF_ADDR_MASK=0x0000000000000FFF,PF3_VF_ADDR_MASK=0x0000000000000FFF,C_PCIEBAR2AXIBAR_0=0x0000000000000000,C_PCIEBAR2AXIBAR_1=0x0000000000000000,C_PCIEBAR2AXIBAR_2=0x0000000000000000,C_PCIEBAR2AXIBAR_3=0x0000000000000000,C_PCIEBAR2AXIBAR_4=0x0000000000000000,C_PCIEBAR2AXIBAR_5=0x0000000000000000,C_PCIEBAR2AXIBAR_6=0x0000000000000000,PF1_BAR0_APERTURE_SIZE=0x00,PF1_BAR1_APERTURE_SIZE=0x00,PF1_BAR2_APERTURE_SIZE=0x00,PF1_BAR3_APERTURE_SIZE=0x00,PF1_BAR4_APERTURE_SIZE=0x00,PF1_BAR5_APERTURE_SIZE=0x00,PF1_BAR6_APERTURE_SIZE=0x00,PF1_BAR0_CONTROL=0x0,PF1_BAR1_CONTROL=0x0,PF1_BAR2_CONTROL=0x0,PF1_BAR3_CONTROL=0x0,PF1_BAR4_CONTROL=0x0,PF1_BAR5_CONTROL=0x0,PF1_BAR6_CONTROL=0x0,PF1_SRIOV_BAR0_CONTROL=0x0,PF1_SRIOV_BAR1_CONTROL=0x0,PF1_SRIOV_BAR2_CONTROL=0x0,PF1_SRIOV_BAR3_CONTROL=0x0,PF1_SRIOV_BAR4_CONTROL=0x0,PF1_SRIOV_BAR5_CONTROL=0x0,PF1_PCIEBAR2AXIBAR_0=0x0000000000000000,PF1_PCIEBAR2AXIBAR_1=0x0000000010000000,PF1_PCIEBAR2AXIBAR_2=0x0000000010000000,PF1_PCIEBAR2AXIBAR_3=0x0000000000000000,PF1_PCIEBAR2AXIBAR_4=0x0000000000000000,PF1_PCIEBAR2AXIBAR_5=0x0000000000000000,PF1_PCIEBAR2AXIBAR_6=0x0000000000000000,PF2_BAR0_APERTURE_SIZE=0x00,PF2_BAR1_APERTURE_SIZE=0x00,PF2_BAR2_APERTURE_SIZE=0x00,PF2_BAR3_APERTURE_SIZE=0x00,PF2_BAR4_APERTURE_SIZE=0x00,PF2_BAR5_APERTURE_SIZE=0x00,PF2_BAR6_APERTURE_SIZE=0x00,PF2_BAR0_CONTROL=0x0,PF2_BAR1_CONTROL=0x0,PF2_BAR2_CONTROL=0x0,PF2_BAR3_CONTROL=0x0,PF2_BAR4_CONTROL=0x0,PF2_BAR5_CONTROL=0x0,PF2_BAR6_CONTROL=0x0,PF2_SRIOV_BAR0_CONTROL=0x0,PF2_SRIOV_BAR1_CONTROL=0x0,PF2_SRIOV_BAR2_CONTROL=0x0,PF2_SRIOV_BAR3_CONTROL=0x0,PF2_SRIOV_BAR4_CONTROL=0x0,PF2_SRIOV_BAR5_CONTROL=0x0,PF2_PCIEBAR2AXIBAR_0=0x0000000000000000,PF2_PCIEBAR2AXIBAR_1=0x0000000020000000,PF2_PCIEBAR2AXIBAR_2=0x0000000020000000,PF2_PCIEBAR2AXIBAR_3=0x0000000000000000,PF2_PCIEBAR2AXIBAR_4=0x0000000000000000,PF2_PCIEBAR2AXIBAR_5=0x0000000000000000,PF2_PCIEBAR2AXIBAR_6=0x0000000000000000,PF3_BAR0_APERTURE_SIZE=0x00,PF3_BAR1_APERTURE_SIZE=0x00,PF3_BAR2_APERTURE_SIZE=0x00,PF3_BAR3_APERTURE_SIZE=0x00,PF3_BAR4_APERTURE_SIZE=0x00,PF3_BAR5_APERTURE_SIZE=0x00,PF3_BAR6_APERTURE_SIZE=0x00,PF3_BAR0_CONTROL=0x0,PF3_BAR1_CONTROL=0x0,PF3_BAR2_CONTROL=0x0,PF3_BAR3_CONTROL=0x0,PF3_BAR4_CONTROL=0x0,PF3_BAR5_CONTROL=0x0,PF3_BAR6_CONTROL=0x0,PF3_SRIOV_BAR0_CONTROL=0x0,PF3_SRIOV_BAR1_CONTROL=0x0,PF3_SRIOV_BAR2_CONTROL=0x0,PF3_SRIOV_BAR3_CONTROL=0x0,PF3_SRIOV_BAR4_CONTROL=0x0,PF3_SRIOV_BAR5_CONTROL=0x0,PF3_PCIEBAR2AXIBAR_0=0x0000000000000000,PF3_PCIEBAR2AXIBAR_1=0x0000000030000000,PF3_PCIEBAR2AXIBAR_2=0x0000000030000000,PF3_PCIEBAR2AXIBAR_3=0x0000000000000000,PF3_PCIEBAR2AXIBAR_4=0x0000000000000000,PF3_PCIEBAR2AXIBAR_5=0x0000000000000000,PF3_PCIEBAR2AXIBAR_6=0x0000000000000000,PF0_VF_BAR0_APERTURE_SIZE=0x00,PF0_VF_BAR1_APERTURE_SIZE=0x00,PF0_VF_BAR2_APERTURE_SIZE=0x00,PF0_VF_BAR3_APERTURE_SIZE=0x00,PF0_VF_BAR4_APERTURE_SIZE=0x00,PF0_VF_BAR5_APERTURE_SIZE=0x00,PF0_VF_BAR6_APERTURE_SIZE=0x00,PF1_VF_BAR0_APERTURE_SIZE=0x00,PF1_VF_BAR1_APERTURE_SIZE=0x00,PF1_VF_BAR2_APERTURE_SIZE=0x00,PF1_VF_BAR3_APERTURE_SIZE=0x00,PF1_VF_BAR4_APERTURE_SIZE=0x00,PF1_VF_BAR5_APERTURE_SIZE=0x00,PF1_VF_BAR6_APERTURE_SIZE=0x00,PF2_VF_BAR0_APERTURE_SIZE=0x00,PF2_VF_BAR1_APERTURE_SIZE=0x00,PF2_VF_BAR2_APERTURE_SIZE=0x00,PF2_VF_BAR3_APERTURE_SIZE=0x00,PF2_VF_BAR4_APERTURE_SIZE=0x00,PF2_VF_BAR5_APERTURE_SIZE=0x00,PF2_VF_BAR6_APERTURE_SIZE=0x00,PF3_VF_BAR0_APERTURE_SIZE=0x00,PF3_VF_BAR1_APERTURE_SIZE=0x00,PF3_VF_BAR2_APERTURE_SIZE=0x00,PF3_VF_BAR3_APERTURE_SIZE=0x00,PF3_VF_BAR4_APERTURE_SIZE=0x00,PF3_VF_BAR5_APERTURE_SIZE=0x00,PF3_VF_BAR6_APERTURE_SIZE=0x00,PF0_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_1=0x0000000040000000,PF0_VF_PCIEBAR2AXIBAR_2=0x0000000040000000,PF0_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_1=0x0000000050000000,PF1_VF_PCIEBAR2AXIBAR_2=0x0000000050000000,PF1_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_1=0x0000000060000000,PF2_VF_PCIEBAR2AXIBAR_2=0x0000000060000000,PF2_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_1=0x0000000070000000,PF3_VF_PCIEBAR2AXIBAR_2=0x0000000070000000,PF3_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,BARLITE1=1,BARLITE2=7,BARLITE_MB_PF0=0,BARLITE_MB_PF1=0,BARLITE_MB_PF2=0,BARLITE_MB_PF3=0,BARLITE_MSIX_PF0=000001,BARLITE_MSIX_PF1=0x00,BARLITE_MSIX_PF2=0x00,BARLITE_MSIX_PF3=0x00,VCU118_BOARD=FALSE,SPLIT_DMA=FALSE,PIPE_LINE_STAGE=2,MULT_PF_DES=FALSE,xlnx_ref_board=None,GTWIZ_IN_CORE=1,GTCOM_IN_CORE=2,INS_LOSS_PROFILE=Add-in_Card,FUNC_MODE=1,PF1_ENABLED=0,PF2_ENABLED=0,PF3_ENABLED=0,DMA_RESET_SOURCE_SEL=0,C_MSIX_INT_TABLE_EN=0,VU9P_TUL_EX=FALSE,XLNX_DDR_EX=FALSE,PCIE_BLK_TYPE=0,CCIX_ENABLE=FALSE,CCIX_DVSEC=FALSE,EXT_SYS_CLK_BUFG=FALSE,C_NUM_OF_SC=1,USR_IRQ_EXDES=FALSE,AXI_VIP_IN_EXDES=FALSE,XDMA_NON_INCREMENTAL_EXDES=FALSE,XDMA_ST_INFINITE_DESC_EXDES=FALSE,EXT_XVC_VSEC_ENABLE=FALSE,ACS_EXT_CAP_ENABLE=FALSE,EN_PCIE_DEBUG_PORTS=FALSE,MULTQ_EN=1,DMA_MM=1,DMA_ST=0,DMA_COMPLETION=0,C_PCIE_PFS_SUPPORTED=1,C_SRIOV_EN=0,BARLITE_EXT_PF0=0x04,BARLITE_EXT_PF1=000000,BARLITE_EXT_PF2=000000,BARLITE_EXT_PF3=000000,BARLITE_INT_PF0=000001,BARLITE_INT_PF1=0x00,BARLITE_INT_PF2=0x00,BARLITE_INT_PF3=0x00,CSR_MODULE=1,NUM_VFS_PF0=4,NUM_VFS_PF1=4,NUM_VFS_PF2=4,NUM_VFS_PF3=4,FIRSTVF_OFFSET_PF0=1,FIRSTVF_OFFSET_PF1=4,FIRSTVF_OFFSET_PF2=7,FIRSTVF_OFFSET_PF3=10,VF_BARLITE_EXT_PF0=0x00,VF_BARLITE_EXT_PF1=0x00,VF_BARLITE_EXT_PF2=0x00,VF_BARLITE_EXT_PF3=0x00,VF_BARLITE_INT_PF0=0x00,VF_BARLITE_INT_PF1=0x00,VF_BARLITE_INT_PF2=0x00,VF_BARLITE_INT_PF3=0x00,C_C2H_NUM_CHNL=4,C_H2C_NUM_CHNL=4,H2C_XDMA_CHNL=0x01,C2H_XDMA_CHNL=0x01,AXISTEN_IF_ENABLE_MSG_ROUTE=0x1EFFF,ENABLE_MORE=FALSE,DISABLE_BRAM_PIPELINE=FALSE,DISABLE_EQ_SYNCHRONIZER=FALSE,C_ENABLE_RESOURCE_REDUCTION=FALSE,GEN4_EIEOS_0S7=TRUE,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_MAX_NUM_QUEUE=512,DSC_BYPASS_RD_CSR=1,DSC_BYPASS_WR_CSR=1,ENABLE_ATS_SWITCH=FALSE,BRIDGE_BURST=FALSE,RQ_RCFG_EN=TRUE,DMA_MODE_EN=FALSE,FLR_ENABLE=FALSE,MAILBOX_ENABLE=FALSE,CFG_SPACE_ENABLE=FALSE,C_LAST_CORE_CAP_ADDR=0x100,C_VSEC_CAP_ADDR=0xE00,CMP_COL_REG_0=1,CMP_COL_REG_1=0,CMP_COL_REG_2=0,CMP_COL_REG_3=0,CMP_COL_REG_4=0,CMP_COL_REG_5=0,CMP_COL_REG_6=0,CMP_COL_REG_7=0,CMP_ERR_REG_0=2,CMP_ERR_REG_1=0,CMP_ERR_REG_2=0,CMP_ERR_REG_3=0,CMP_ERR_REG_4=0,CMP_ERR_REG_5=0,CMP_ERR_REG_6=0,CMP_ERR_REG_7=0,C2H_STREAM_CPL_DATA_SIZE=0,ARI_CAP_ENABLE=false,AXISTEN_IF_MSIX_RX_PARITY_EN=FALSE,PF0_MSIX_VECTORS=1,PF1_MSIX_VECTORS=8,PF2_MSIX_VECTORS=0,PF3_MSIX_VECTORS=0,ADV_INT_USR=FALSE,PCIE_ID_IF=FALSE,MDMA_PFCH_CACHE_DEPTH=16,WRB_COAL_MAX_BUF=16,ENABLE_ERROR_INJECTION=FALSE,ENABLE_AT_PORTS=FALSE,WRB_COAL_LOOP_FIX_DISABLE=0,USE_STANDARD_INTERFACES=TRUE,DMA_2RP=FALSE,VIRTIO_EN=FALSE,MHOST_EN=FALSE,ALF_CAP_ENABLE=FALSE,ASYNC_CLK_ENABLE=FALSE,SOFT_NIC=FALSE,VDM_EN=FALSE,C_M_AXIB_EN=FALSE,SOFT_NIC_BRIDGE=FALSE,USR_IRQ_XDMA_TYPE_INTERFACE=FALSE,C_DBG_EN=DEBUG_NONE,C_DSC_BYP_MODE=NONE,IEP_EN=FALSE,SHELL_BRIDGE=0,MSIX_PCIE_INTERNAL=0,C_AXIBAR_NOTRANSLATE=0,VERSAL_PART_TYPE=SXX,VERSAL_PART_TYPE_HXX=NVD,DATA_MOVER=FALSE,TANDEM_RFSOC=FALSE,PL_DISABLE_LANE_REVERSAL=TRUE,ENABLE_64BIT=TRUE}" *) (* DowngradeIPIdentifiedWarnings = "yes" *)
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/AS02MC04_qdma_enum_qdma_0_0_stub.vhdl (1 usage)
-(124, 11747) attribute CORE_GENERATION_INFO of AS02MC04_qdma_enum_qdma_0_0 : entity is "AS02MC04_qdma_enum_qdma_0_0,AS02MC04_qdma_enum_qdma_0_0_core_top,{x_ipProduct=Vivado 2025.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=qdma,x_ipVersion=5.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,PL_UPSTREAM_FACING=true,TL_LEGACY_MODE_ENABLE=false,PCIE_BLK_LOCN=0,PL_LINK_CAP_MAX_LINK_WIDTH=8,PL_LINK_CAP_MAX_LINK_SPEED=4,REF_CLK_FREQ=0,DRP_CLK_SEL=0,FREE_RUN_FREQ=0,AXI_ADDR_WIDTH=64,AXI_DATA_WIDTH=256,CORE_CLK_FREQ=1,PLL_TYPE=2,USER_CLK_FREQ=2,SILICON_REV=Pre-Production,PIPE_SIM=FALSE,EGW_IS_PARENT_IP=1,EXT_CH_GT_DRP=false,PCIE3_DRP=false,DEDICATE_PERST=true,SYS_RESET_POLARITY=0,MCAP_ENABLEMENT=NONE,EXT_STARTUP_PRIMITIVE=false,RBAR_ENABLE=FALSE,PF0_VENDOR_ID=0x10EE,PF0_DEVICE_ID=0x9038,PF0_REVISION_ID=0x00,PF0_SUBSYSTEM_VENDOR_ID=0x0002,PF0_SUBSYSTEM_ID=0x002A,PF1_VENDOR_ID=0x10EE,PF1_DEVICE_ID=0x913F,PF1_REVISION_ID=0x00,PF1_SUBSYSTEM_VENDOR_ID=0x0002,PF1_SUBSYSTEM_ID=0x0007,PF2_VENDOR_ID=0x10EE,PF2_DEVICE_ID=0x9238,PF2_REVISION_ID=0x00,PF2_SUBSYSTEM_VENDOR_ID=0x10EE,PF2_SUBSYSTEM_ID=0x0007,PF3_VENDOR_ID=0x10EE,PF3_DEVICE_ID=0x9338,PF3_REVISION_ID=0x00,PF3_SUBSYSTEM_VENDOR_ID=0x10EE,PF3_SUBSYSTEM_ID=0x0007,AXILITE_MASTER_APERTURE_SIZE=0x0D,AXILITE_MASTER_CONTROL=0x4,XDMA_APERTURE_SIZE=0x0D,XDMA_CONTROL=0x4,AXIST_BYPASS_APERTURE_SIZE=0x00,AXIST_BYPASS_CONTROL=0x0,PF0_INTERRUPT_PIN=0x1,PF1_INTERRUPT_PIN=0x1,PF2_INTERRUPT_PIN=0x1,PF3_INTERRUPT_PIN=0x1,PF0_MSI_CAP_MULTIMSGCAP=0,C_COMP_TIMEOUT=1,C_TIMEOUT0_SEL=0xE,C_TIMEOUT1_SEL=0xF,C_TIMEOUT_MULT=0x3,C_OLD_BRIDGE_TIMEOUT=0,SHARED_LOGIC=1,SHARED_LOGIC_CLK=false,SHARED_LOGIC_BOTH=false,SHARED_LOGIC_GTC=false,EN_TRANSCEIVER_STATUS_PORTS=FALSE,IS_BOARD_PROJECT=0,EN_GT_SELECTION=FALSE,SELECT_QUAD=GTY_Quad_227,ULTRASCALE=FALSE,ULTRASCALE_PLUS=TRUE,VERSAL=FALSE,V7_GEN3=FALSE,MSI_ENABLED=FALSE,RP_MSI_ENABLED=TRUE,DEV_PORT_TYPE=0,XDMA_AXI_INTF_MM=1,XDMA_PCIE_64BIT_EN=false,XDMA_AXILITE_MASTER=TRUE,XDMA_AXIST_BYPASS=FALSE,XDMA_RNUM_CHNL=4,XDMA_WNUM_CHNL=4,XDMA_AXILITE_SLAVE=FALSE,CSR_AXILITE_SLAVE=FALSE,XDMA_NUM_USR_IRQ=16,XDMA_RNUM_RIDS=32,XDMA_WNUM_RIDS=32,C_M_AXI_ID_WIDTH=4,C_AXIBAR_NUM=1,C_FAMILY=kintexuplus,XDMA_NUM_PCIE_TAG=256,EN_AXI_MASTER_IF=FALSE,XDMA_DSC_BYPASS=FALSE,C_METERING_ON=1,RX_DETECT=0,C_ATS_ENABLE=FALSE,C_ATS_CAP_NEXTPTR=0x000,C_PR_CAP_NEXTPTR=0x000,C_PRI_ENABLE=FALSE,DSC_BYPASS_RD=0,DSC_BYPASS_WR=0,DSC_BYPASS_RD_OUT=0,DSC_BYPASS_WR_OUT=0,XDMA_STS_PORTS=FALSE,MSIX_ENABLED=TRUE,CFG_MGMT_IF=TRUE,RQ_SEQ_NUM_IGNORE=0,CFG_EXT_IF=FALSE,LEGACY_CFG_EXT_IF=FALSE,C_PARITY_PROP=0,EN_DEBUG_PORTS=FALSE,VU9P_BOARD=FALSE,ENABLE_JTAG_DBG=TRUE,ENABLE_IBERT=FALSE,MM_SLAVE_EN=0,DMA_EN=1,C_AXIBAR_0=0x0000000000000000,C_AXIBAR_1=0x0000000000000000,C_AXIBAR_2=0x0000000000000000,C_AXIBAR_3=0x0000000000000000,C_AXIBAR_4=0x0000000000000000,C_AXIBAR_5=0x0000000000000000,C_AXIBAR_HIGHADDR_0=0x0000000000000000,C_AXIBAR_HIGHADDR_1=0x0000000000000000,C_AXIBAR_HIGHADDR_2=0x0000000000000000,C_AXIBAR_HIGHADDR_3=0x0000000000000000,C_AXIBAR_HIGHADDR_4=0x0000000000000000,C_AXIBAR_HIGHADDR_5=0x0000000000000000,C_AXIBAR2PCIEBAR_0=0x0000000000000000,C_AXIBAR2PCIEBAR_1=0x0000000000000000,C_AXIBAR2PCIEBAR_2=0x0000000000000000,C_AXIBAR2PCIEBAR_3=0x0000000000000000,C_AXIBAR2PCIEBAR_4=0x0000000000000000,C_AXIBAR2PCIEBAR_5=0x0000000000000000,MINIMAL_DMA_EN=FALSE,EN_AXI_SLAVE_IF=TRUE,C_INCLUDE_BAROFFSET_REG=1,C_BASEADDR=0x00001000,C_HIGHADDR=0x00001FFF,C_S_AXI_ID_WIDTH=4,C_S_AXI_NUM_READ=32,C_M_AXI_NUM_READ=32,C_S_AXI_NUM_WRITE=32,C_M_AXI_NUM_WRITE=16,MSIX_IMPL_EXT=TRUE,AXI_ACLK_LOOPBACK=FALSE,PCIEBAR_NUM=6,PF0_BAR0_APERTURE_SIZE=0x0B,PF0_BAR1_APERTURE_SIZE=0x00,PF0_BAR2_APERTURE_SIZE=0x05,PF0_BAR3_APERTURE_SIZE=0x00,PF0_BAR4_APERTURE_SIZE=0x00,PF0_BAR5_APERTURE_SIZE=0x00,PF0_BAR6_APERTURE_SIZE=0x00,PF0_BAR0_CONTROL=0x6,PF0_BAR1_CONTROL=0x0,PF0_BAR2_CONTROL=0x6,PF0_BAR3_CONTROL=0x0,PF0_BAR4_CONTROL=0x0,PF0_BAR5_CONTROL=0x0,PF0_BAR6_CONTROL=0x0,PF0_SRIOV_BAR0_CONTROL=0x7,PF0_SRIOV_BAR1_CONTROL=0x0,PF0_SRIOV_BAR2_CONTROL=0x7,PF0_SRIOV_BAR3_CONTROL=0x0,PF0_SRIOV_BAR4_CONTROL=0x0,PF0_SRIOV_BAR5_CONTROL=0x0,PF0_ADDR_MASK=0x0000000000000FFF,PF1_ADDR_MASK=0x0000000000000FFF,PF2_ADDR_MASK=0x0000000000000FFF,PF3_ADDR_MASK=0x0000000000000FFF,PF0_VF_ADDR_MASK=0x0000000000000FFF,PF1_VF_ADDR_MASK=0x0000000000000FFF,PF2_VF_ADDR_MASK=0x0000000000000FFF,PF3_VF_ADDR_MASK=0x0000000000000FFF,C_PCIEBAR2AXIBAR_0=0x0000000000000000,C_PCIEBAR2AXIBAR_1=0x0000000000000000,C_PCIEBAR2AXIBAR_2=0x0000000000000000,C_PCIEBAR2AXIBAR_3=0x0000000000000000,C_PCIEBAR2AXIBAR_4=0x0000000000000000,C_PCIEBAR2AXIBAR_5=0x0000000000000000,C_PCIEBAR2AXIBAR_6=0x0000000000000000,PF1_BAR0_APERTURE_SIZE=0x00,PF1_BAR1_APERTURE_SIZE=0x00,PF1_BAR2_APERTURE_SIZE=0x00,PF1_BAR3_APERTURE_SIZE=0x00,PF1_BAR4_APERTURE_SIZE=0x00,PF1_BAR5_APERTURE_SIZE=0x00,PF1_BAR6_APERTURE_SIZE=0x00,PF1_BAR0_CONTROL=0x0,PF1_BAR1_CONTROL=0x0,PF1_BAR2_CONTROL=0x0,PF1_BAR3_CONTROL=0x0,PF1_BAR4_CONTROL=0x0,PF1_BAR5_CONTROL=0x0,PF1_BAR6_CONTROL=0x0,PF1_SRIOV_BAR0_CONTROL=0x0,PF1_SRIOV_BAR1_CONTROL=0x0,PF1_SRIOV_BAR2_CONTROL=0x0,PF1_SRIOV_BAR3_CONTROL=0x0,PF1_SRIOV_BAR4_CONTROL=0x0,PF1_SRIOV_BAR5_CONTROL=0x0,PF1_PCIEBAR2AXIBAR_0=0x0000000000000000,PF1_PCIEBAR2AXIBAR_1=0x0000000010000000,PF1_PCIEBAR2AXIBAR_2=0x0000000010000000,PF1_PCIEBAR2AXIBAR_3=0x0000000000000000,PF1_PCIEBAR2AXIBAR_4=0x0000000000000000,PF1_PCIEBAR2AXIBAR_5=0x0000000000000000,PF1_PCIEBAR2AXIBAR_6=0x0000000000000000,PF2_BAR0_APERTURE_SIZE=0x00,PF2_BAR1_APERTURE_SIZE=0x00,PF2_BAR2_APERTURE_SIZE=0x00,PF2_BAR3_APERTURE_SIZE=0x00,PF2_BAR4_APERTURE_SIZE=0x00,PF2_BAR5_APERTURE_SIZE=0x00,PF2_BAR6_APERTURE_SIZE=0x00,PF2_BAR0_CONTROL=0x0,PF2_BAR1_CONTROL=0x0,PF2_BAR2_CONTROL=0x0,PF2_BAR3_CONTROL=0x0,PF2_BAR4_CONTROL=0x0,PF2_BAR5_CONTROL=0x0,PF2_BAR6_CONTROL=0x0,PF2_SRIOV_BAR0_CONTROL=0x0,PF2_SRIOV_BAR1_CONTROL=0x0,PF2_SRIOV_BAR2_CONTROL=0x0,PF2_SRIOV_BAR3_CONTROL=0x0,PF2_SRIOV_BAR4_CONTROL=0x0,PF2_SRIOV_BAR5_CONTROL=0x0,PF2_PCIEBAR2AXIBAR_0=0x0000000000000000,PF2_PCIEBAR2AXIBAR_1=0x0000000020000000,PF2_PCIEBAR2AXIBAR_2=0x0000000020000000,PF2_PCIEBAR2AXIBAR_3=0x0000000000000000,PF2_PCIEBAR2AXIBAR_4=0x0000000000000000,PF2_PCIEBAR2AXIBAR_5=0x0000000000000000,PF2_PCIEBAR2AXIBAR_6=0x0000000000000000,PF3_BAR0_APERTURE_SIZE=0x00,PF3_BAR1_APERTURE_SIZE=0x00,PF3_BAR2_APERTURE_SIZE=0x00,PF3_BAR3_APERTURE_SIZE=0x00,PF3_BAR4_APERTURE_SIZE=0x00,PF3_BAR5_APERTURE_SIZE=0x00,PF3_BAR6_APERTURE_SIZE=0x00,PF3_BAR0_CONTROL=0x0,PF3_BAR1_CONTROL=0x0,PF3_BAR2_CONTROL=0x0,PF3_BAR3_CONTROL=0x0,PF3_BAR4_CONTROL=0x0,PF3_BAR5_CONTROL=0x0,PF3_BAR6_CONTROL=0x0,PF3_SRIOV_BAR0_CONTROL=0x0,PF3_SRIOV_BAR1_CONTROL=0x0,PF3_SRIOV_BAR2_CONTROL=0x0,PF3_SRIOV_BAR3_CONTROL=0x0,PF3_SRIOV_BAR4_CONTROL=0x0,PF3_SRIOV_BAR5_CONTROL=0x0,PF3_PCIEBAR2AXIBAR_0=0x0000000000000000,PF3_PCIEBAR2AXIBAR_1=0x0000000030000000,PF3_PCIEBAR2AXIBAR_2=0x0000000030000000,PF3_PCIEBAR2AXIBAR_3=0x0000000000000000,PF3_PCIEBAR2AXIBAR_4=0x0000000000000000,PF3_PCIEBAR2AXIBAR_5=0x0000000000000000,PF3_PCIEBAR2AXIBAR_6=0x0000000000000000,PF0_VF_BAR0_APERTURE_SIZE=0x00,PF0_VF_BAR1_APERTURE_SIZE=0x00,PF0_VF_BAR2_APERTURE_SIZE=0x00,PF0_VF_BAR3_APERTURE_SIZE=0x00,PF0_VF_BAR4_APERTURE_SIZE=0x00,PF0_VF_BAR5_APERTURE_SIZE=0x00,PF0_VF_BAR6_APERTURE_SIZE=0x00,PF1_VF_BAR0_APERTURE_SIZE=0x00,PF1_VF_BAR1_APERTURE_SIZE=0x00,PF1_VF_BAR2_APERTURE_SIZE=0x00,PF1_VF_BAR3_APERTURE_SIZE=0x00,PF1_VF_BAR4_APERTURE_SIZE=0x00,PF1_VF_BAR5_APERTURE_SIZE=0x00,PF1_VF_BAR6_APERTURE_SIZE=0x00,PF2_VF_BAR0_APERTURE_SIZE=0x00,PF2_VF_BAR1_APERTURE_SIZE=0x00,PF2_VF_BAR2_APERTURE_SIZE=0x00,PF2_VF_BAR3_APERTURE_SIZE=0x00,PF2_VF_BAR4_APERTURE_SIZE=0x00,PF2_VF_BAR5_APERTURE_SIZE=0x00,PF2_VF_BAR6_APERTURE_SIZE=0x00,PF3_VF_BAR0_APERTURE_SIZE=0x00,PF3_VF_BAR1_APERTURE_SIZE=0x00,PF3_VF_BAR2_APERTURE_SIZE=0x00,PF3_VF_BAR3_APERTURE_SIZE=0x00,PF3_VF_BAR4_APERTURE_SIZE=0x00,PF3_VF_BAR5_APERTURE_SIZE=0x00,PF3_VF_BAR6_APERTURE_SIZE=0x00,PF0_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_1=0x0000000040000000,PF0_VF_PCIEBAR2AXIBAR_2=0x0000000040000000,PF0_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_1=0x0000000050000000,PF1_VF_PCIEBAR2AXIBAR_2=0x0000000050000000,PF1_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_1=0x0000000060000000,PF2_VF_PCIEBAR2AXIBAR_2=0x0000000060000000,PF2_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_1=0x0000000070000000,PF3_VF_PCIEBAR2AXIBAR_2=0x0000000070000000,PF3_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,BARLITE1=1,BARLITE2=7,BARLITE_MB_PF0=0,BARLITE_MB_PF1=0,BARLITE_MB_PF2=0,BARLITE_MB_PF3=0,BARLITE_MSIX_PF0=000001,BARLITE_MSIX_PF1=0x00,BARLITE_MSIX_PF2=0x00,BARLITE_MSIX_PF3=0x00,VCU118_BOARD=FALSE,SPLIT_DMA=FALSE,PIPE_LINE_STAGE=2,MULT_PF_DES=FALSE,xlnx_ref_board=None,GTWIZ_IN_CORE=1,GTCOM_IN_CORE=2,INS_LOSS_PROFILE=Add-in_Card,FUNC_MODE=1,PF1_ENABLED=0,PF2_ENABLED=0,PF3_ENABLED=0,DMA_RESET_SOURCE_SEL=0,C_MSIX_INT_TABLE_EN=0,VU9P_TUL_EX=FALSE,XLNX_DDR_EX=FALSE,PCIE_BLK_TYPE=0,CCIX_ENABLE=FALSE,CCIX_DVSEC=FALSE,EXT_SYS_CLK_BUFG=FALSE,C_NUM_OF_SC=1,USR_IRQ_EXDES=FALSE,AXI_VIP_IN_EXDES=FALSE,XDMA_NON_INCREMENTAL_EXDES=FALSE,XDMA_ST_INFINITE_DESC_EXDES=FALSE,EXT_XVC_VSEC_ENABLE=FALSE,ACS_EXT_CAP_ENABLE=FALSE,EN_PCIE_DEBUG_PORTS=FALSE,MULTQ_EN=1,DMA_MM=1,DMA_ST=0,DMA_COMPLETION=0,C_PCIE_PFS_SUPPORTED=1,C_SRIOV_EN=0,BARLITE_EXT_PF0=0x04,BARLITE_EXT_PF1=000000,BARLITE_EXT_PF2=000000,BARLITE_EXT_PF3=000000,BARLITE_INT_PF0=000001,BARLITE_INT_PF1=0x00,BARLITE_INT_PF2=0x00,BARLITE_INT_PF3=0x00,CSR_MODULE=1,NUM_VFS_PF0=4,NUM_VFS_PF1=4,NUM_VFS_PF2=4,NUM_VFS_PF3=4,FIRSTVF_OFFSET_PF0=1,FIRSTVF_OFFSET_PF1=4,FIRSTVF_OFFSET_PF2=7,FIRSTVF_OFFSET_PF3=10,VF_BARLITE_EXT_PF0=0x00,VF_BARLITE_EXT_PF1=0x00,VF_BARLITE_EXT_PF2=0x00,VF_BARLITE_EXT_PF3=0x00,VF_BARLITE_INT_PF0=0x00,VF_BARLITE_INT_PF1=0x00,VF_BARLITE_INT_PF2=0x00,VF_BARLITE_INT_PF3=0x00,C_C2H_NUM_CHNL=4,C_H2C_NUM_CHNL=4,H2C_XDMA_CHNL=0x01,C2H_XDMA_CHNL=0x01,AXISTEN_IF_ENABLE_MSG_ROUTE=0x1EFFF,ENABLE_MORE=FALSE,DISABLE_BRAM_PIPELINE=FALSE,DISABLE_EQ_SYNCHRONIZER=FALSE,C_ENABLE_RESOURCE_REDUCTION=FALSE,GEN4_EIEOS_0S7=TRUE,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_MAX_NUM_QUEUE=512,DSC_BYPASS_RD_CSR=1,DSC_BYPASS_WR_CSR=1,ENABLE_ATS_SWITCH=FALSE,BRIDGE_BURST=FALSE,RQ_RCFG_EN=TRUE,DMA_MODE_EN=FALSE,FLR_ENABLE=FALSE,MAILBOX_ENABLE=FALSE,CFG_SPACE_ENABLE=FALSE,C_LAST_CORE_CAP_ADDR=0x100,C_VSEC_CAP_ADDR=0xE00,CMP_COL_REG_0=1,CMP_COL_REG_1=0,CMP_COL_REG_2=0,CMP_COL_REG_3=0,CMP_COL_REG_4=0,CMP_COL_REG_5=0,CMP_COL_REG_6=0,CMP_COL_REG_7=0,CMP_ERR_REG_0=2,CMP_ERR_REG_1=0,CMP_ERR_REG_2=0,CMP_ERR_REG_3=0,CMP_ERR_REG_4=0,CMP_ERR_REG_5=0,CMP_ERR_REG_6=0,CMP_ERR_REG_7=0,C2H_STREAM_CPL_DATA_SIZE=0,ARI_CAP_ENABLE=false,AXISTEN_IF_MSIX_RX_PARITY_EN=FALSE,PF0_MSIX_VECTORS=1,PF1_MSIX_VECTORS=8,PF2_MSIX_VECTORS=0,PF3_MSIX_VECTORS=0,ADV_INT_USR=FALSE,PCIE_ID_IF=FALSE,MDMA_PFCH_CACHE_DEPTH=16,WRB_COAL_MAX_BUF=16,ENABLE_ERROR_INJECTION=FALSE,ENABLE_AT_PORTS=FALSE,WRB_COAL_LOOP_FIX_DISABLE=0,USE_STANDARD_INTERFACES=TRUE,DMA_2RP=FALSE,VIRTIO_EN=FALSE,MHOST_EN=FALSE,ALF_CAP_ENABLE=FALSE,ASYNC_CLK_ENABLE=FALSE,SOFT_NIC=FALSE,VDM_EN=FALSE,C_M_AXIB_EN=FALSE,SOFT_NIC_BRIDGE=FALSE,USR_IRQ_XDMA_TYPE_INTERFACE=FALSE,C_DBG_EN=DEBUG_NONE,C_DSC_BYP_MODE=NONE,IEP_EN=FALSE,SHELL_BRIDGE=0,MSIX_PCIE_INTERNAL=0,C_AXIBAR_NOTRANSLATE=0,VERSAL_PART_TYPE=SXX,VERSAL_PART_TYPE_HXX=NVD,DATA_MOVER=FALSE,TANDEM_RFSOC=FALSE,PL_DISABLE_LANE_REVERSAL=TRUE,ENABLE_64BIT=TRUE}";
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/synth/AS02MC04_qdma_enum_qdma_0_0.sv (2 usages)
-(78, 170) ONE,IEP_EN=FALSE,SHELL_BRIDGE=0,MSIX_PCIE_INTERNAL=0,C_AXIBAR_NOTRANSLATE=0,VERSAL_PART_TYPE=SXX,VERSAL_PART_TYPE_HXX=NVD,DATA_MOVER=FALSE,TANDEM_RFSOC=FALSE,PL_DISABLE_LANE_REVERSAL=TRUE,ENABLE_64BIT=TRUE}" *)
-(866, 17) .PL_DISABLE_LANE_REVERSAL("TRUE"),
-/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/hw_handoff/AS02MC04_qdma_enum.hwh (3 usages)
-(676, 37) <PARAMETER NAME="PL_DISABLE_LANE_REVERSAL" VALUE="TRUE"/>
-(796, 37) <PARAMETER NAME="PL_DISABLE_LANE_REVERSAL_NV" VALUE="true"/>
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/sim/AS02MC04_qdma_enum_qdma_0_0.sv (1 usage)
+(842, 17) .PL_DISABLE_LANE_REVERSAL("FALSE"),
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/AS02MC04_qdma_enum_qdma_0_0_stub.v (1 usage)
+(17, 11794) (* CHECK_LICENSE_TYPE = "AS02MC04_qdma_enum_qdma_0_0,AS02MC04_qdma_enum_qdma_0_0_core_top,{}" *) (* CORE_GENERATION_INFO = "AS02MC04_qdma_enum_qdma_0_0,AS02MC04_qdma_enum_qdma_0_0_core_top,{x_ipProduct=Vivado 2025.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=qdma,x_ipVersion=5.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,PL_UPSTREAM_FACING=true,TL_LEGACY_MODE_ENABLE=false,PCIE_BLK_LOCN=0,PL_LINK_CAP_MAX_LINK_WIDTH=8,PL_LINK_CAP_MAX_LINK_SPEED=4,REF_CLK_FREQ=0,DRP_CLK_SEL=0,FREE_RUN_FREQ=0,AXI_ADDR_WIDTH=64,AXI_DATA_WIDTH=256,CORE_CLK_FREQ=1,PLL_TYPE=2,USER_CLK_FREQ=2,SILICON_REV=Pre-Production,PIPE_SIM=FALSE,EGW_IS_PARENT_IP=1,EXT_CH_GT_DRP=false,PCIE3_DRP=false,DEDICATE_PERST=true,SYS_RESET_POLARITY=0,MCAP_ENABLEMENT=NONE,EXT_STARTUP_PRIMITIVE=false,RBAR_ENABLE=FALSE,PF0_VENDOR_ID=0x10EE,PF0_DEVICE_ID=0x9038,PF0_REVISION_ID=0x01,PF0_SUBSYSTEM_VENDOR_ID=0x0002,PF0_SUBSYSTEM_ID=0x002A,PF1_VENDOR_ID=0x10EE,PF1_DEVICE_ID=0x913F,PF1_REVISION_ID=0x00,PF1_SUBSYSTEM_VENDOR_ID=0x0002,PF1_SUBSYSTEM_ID=0x0007,PF2_VENDOR_ID=0x10EE,PF2_DEVICE_ID=0x9238,PF2_REVISION_ID=0x00,PF2_SUBSYSTEM_VENDOR_ID=0x10EE,PF2_SUBSYSTEM_ID=0x0007,PF3_VENDOR_ID=0x10EE,PF3_DEVICE_ID=0x9338,PF3_REVISION_ID=0x00,PF3_SUBSYSTEM_VENDOR_ID=0x10EE,PF3_SUBSYSTEM_ID=0x0007,AXILITE_MASTER_APERTURE_SIZE=0x0D,AXILITE_MASTER_CONTROL=0x4,XDMA_APERTURE_SIZE=0x0D,XDMA_CONTROL=0x4,AXIST_BYPASS_APERTURE_SIZE=0x00,AXIST_BYPASS_CONTROL=0x0,PF0_INTERRUPT_PIN=0x1,PF1_INTERRUPT_PIN=0x1,PF2_INTERRUPT_PIN=0x1,PF3_INTERRUPT_PIN=0x1,PF0_MSI_CAP_MULTIMSGCAP=0,C_COMP_TIMEOUT=1,C_TIMEOUT0_SEL=0xE,C_TIMEOUT1_SEL=0xF,C_TIMEOUT_MULT=0x3,C_OLD_BRIDGE_TIMEOUT=0,SHARED_LOGIC=1,SHARED_LOGIC_CLK=false,SHARED_LOGIC_BOTH=false,SHARED_LOGIC_GTC=false,EN_TRANSCEIVER_STATUS_PORTS=FALSE,IS_BOARD_PROJECT=0,EN_GT_SELECTION=FALSE,SELECT_QUAD=GTY_Quad_227,ULTRASCALE=FALSE,ULTRASCALE_PLUS=TRUE,VERSAL=FALSE,V7_GEN3=FALSE,MSI_ENABLED=FALSE,RP_MSI_ENABLED=TRUE,DEV_PORT_TYPE=0,XDMA_AXI_INTF_MM=1,XDMA_PCIE_64BIT_EN=false,XDMA_AXILITE_MASTER=TRUE,XDMA_AXIST_BYPASS=FALSE,XDMA_RNUM_CHNL=4,XDMA_WNUM_CHNL=4,XDMA_AXILITE_SLAVE=FALSE,CSR_AXILITE_SLAVE=FALSE,XDMA_NUM_USR_IRQ=16,XDMA_RNUM_RIDS=32,XDMA_WNUM_RIDS=32,C_M_AXI_ID_WIDTH=4,C_AXIBAR_NUM=1,C_FAMILY=kintexuplus,XDMA_NUM_PCIE_TAG=256,EN_AXI_MASTER_IF=FALSE,XDMA_DSC_BYPASS=FALSE,C_METERING_ON=1,RX_DETECT=0,C_ATS_ENABLE=FALSE,C_ATS_CAP_NEXTPTR=0x000,C_PR_CAP_NEXTPTR=0x000,C_PRI_ENABLE=FALSE,DSC_BYPASS_RD=0,DSC_BYPASS_WR=0,DSC_BYPASS_RD_OUT=0,DSC_BYPASS_WR_OUT=0,XDMA_STS_PORTS=FALSE,MSIX_ENABLED=TRUE,CFG_MGMT_IF=TRUE,RQ_SEQ_NUM_IGNORE=0,CFG_EXT_IF=FALSE,LEGACY_CFG_EXT_IF=FALSE,C_PARITY_PROP=0,EN_DEBUG_PORTS=FALSE,VU9P_BOARD=FALSE,ENABLE_JTAG_DBG=TRUE,ENABLE_IBERT=FALSE,MM_SLAVE_EN=0,DMA_EN=1,C_AXIBAR_0=0x0000000000000000,C_AXIBAR_1=0x0000000000000000,C_AXIBAR_2=0x0000000000000000,C_AXIBAR_3=0x0000000000000000,C_AXIBAR_4=0x0000000000000000,C_AXIBAR_5=0x0000000000000000,C_AXIBAR_HIGHADDR_0=0x0000000000000000,C_AXIBAR_HIGHADDR_1=0x0000000000000000,C_AXIBAR_HIGHADDR_2=0x0000000000000000,C_AXIBAR_HIGHADDR_3=0x0000000000000000,C_AXIBAR_HIGHADDR_4=0x0000000000000000,C_AXIBAR_HIGHADDR_5=0x0000000000000000,C_AXIBAR2PCIEBAR_0=0x0000000000000000,C_AXIBAR2PCIEBAR_1=0x0000000000000000,C_AXIBAR2PCIEBAR_2=0x0000000000000000,C_AXIBAR2PCIEBAR_3=0x0000000000000000,C_AXIBAR2PCIEBAR_4=0x0000000000000000,C_AXIBAR2PCIEBAR_5=0x0000000000000000,MINIMAL_DMA_EN=FALSE,EN_AXI_SLAVE_IF=TRUE,C_INCLUDE_BAROFFSET_REG=1,C_BASEADDR=0x00001000,C_HIGHADDR=0x00001FFF,C_S_AXI_ID_WIDTH=4,C_S_AXI_NUM_READ=32,C_M_AXI_NUM_READ=32,C_S_AXI_NUM_WRITE=32,C_M_AXI_NUM_WRITE=16,MSIX_IMPL_EXT=TRUE,AXI_ACLK_LOOPBACK=FALSE,PCIEBAR_NUM=6,PF0_BAR0_APERTURE_SIZE=0x0B,PF0_BAR1_APERTURE_SIZE=0x00,PF0_BAR2_APERTURE_SIZE=0x05,PF0_BAR3_APERTURE_SIZE=0x00,PF0_BAR4_APERTURE_SIZE=0x00,PF0_BAR5_APERTURE_SIZE=0x00,PF0_BAR6_APERTURE_SIZE=0x00,PF0_BAR0_CONTROL=0x6,PF0_BAR1_CONTROL=0x0,PF0_BAR2_CONTROL=0x6,PF0_BAR3_CONTROL=0x0,PF0_BAR4_CONTROL=0x0,PF0_BAR5_CONTROL=0x0,PF0_BAR6_CONTROL=0x0,PF0_SRIOV_BAR0_CONTROL=0x7,PF0_SRIOV_BAR1_CONTROL=0x0,PF0_SRIOV_BAR2_CONTROL=0x7,PF0_SRIOV_BAR3_CONTROL=0x0,PF0_SRIOV_BAR4_CONTROL=0x0,PF0_SRIOV_BAR5_CONTROL=0x0,PF0_ADDR_MASK=0x0000000000000FFF,PF1_ADDR_MASK=0x0000000000000FFF,PF2_ADDR_MASK=0x0000000000000FFF,PF3_ADDR_MASK=0x0000000000000FFF,PF0_VF_ADDR_MASK=0x0000000000000FFF,PF1_VF_ADDR_MASK=0x0000000000000FFF,PF2_VF_ADDR_MASK=0x0000000000000FFF,PF3_VF_ADDR_MASK=0x0000000000000FFF,C_PCIEBAR2AXIBAR_0=0x0000000000000000,C_PCIEBAR2AXIBAR_1=0x0000000000000000,C_PCIEBAR2AXIBAR_2=0x0000000000000000,C_PCIEBAR2AXIBAR_3=0x0000000000000000,C_PCIEBAR2AXIBAR_4=0x0000000000000000,C_PCIEBAR2AXIBAR_5=0x0000000000000000,C_PCIEBAR2AXIBAR_6=0x0000000000000000,PF1_BAR0_APERTURE_SIZE=0x00,PF1_BAR1_APERTURE_SIZE=0x00,PF1_BAR2_APERTURE_SIZE=0x00,PF1_BAR3_APERTURE_SIZE=0x00,PF1_BAR4_APERTURE_SIZE=0x00,PF1_BAR5_APERTURE_SIZE=0x00,PF1_BAR6_APERTURE_SIZE=0x00,PF1_BAR0_CONTROL=0x0,PF1_BAR1_CONTROL=0x0,PF1_BAR2_CONTROL=0x0,PF1_BAR3_CONTROL=0x0,PF1_BAR4_CONTROL=0x0,PF1_BAR5_CONTROL=0x0,PF1_BAR6_CONTROL=0x0,PF1_SRIOV_BAR0_CONTROL=0x0,PF1_SRIOV_BAR1_CONTROL=0x0,PF1_SRIOV_BAR2_CONTROL=0x0,PF1_SRIOV_BAR3_CONTROL=0x0,PF1_SRIOV_BAR4_CONTROL=0x0,PF1_SRIOV_BAR5_CONTROL=0x0,PF1_PCIEBAR2AXIBAR_0=0x0000000000000000,PF1_PCIEBAR2AXIBAR_1=0x0000000010000000,PF1_PCIEBAR2AXIBAR_2=0x0000000010000000,PF1_PCIEBAR2AXIBAR_3=0x0000000000000000,PF1_PCIEBAR2AXIBAR_4=0x0000000000000000,PF1_PCIEBAR2AXIBAR_5=0x0000000000000000,PF1_PCIEBAR2AXIBAR_6=0x0000000000000000,PF2_BAR0_APERTURE_SIZE=0x00,PF2_BAR1_APERTURE_SIZE=0x00,PF2_BAR2_APERTURE_SIZE=0x00,PF2_BAR3_APERTURE_SIZE=0x00,PF2_BAR4_APERTURE_SIZE=0x00,PF2_BAR5_APERTURE_SIZE=0x00,PF2_BAR6_APERTURE_SIZE=0x00,PF2_BAR0_CONTROL=0x0,PF2_BAR1_CONTROL=0x0,PF2_BAR2_CONTROL=0x0,PF2_BAR3_CONTROL=0x0,PF2_BAR4_CONTROL=0x0,PF2_BAR5_CONTROL=0x0,PF2_BAR6_CONTROL=0x0,PF2_SRIOV_BAR0_CONTROL=0x0,PF2_SRIOV_BAR1_CONTROL=0x0,PF2_SRIOV_BAR2_CONTROL=0x0,PF2_SRIOV_BAR3_CONTROL=0x0,PF2_SRIOV_BAR4_CONTROL=0x0,PF2_SRIOV_BAR5_CONTROL=0x0,PF2_PCIEBAR2AXIBAR_0=0x0000000000000000,PF2_PCIEBAR2AXIBAR_1=0x0000000020000000,PF2_PCIEBAR2AXIBAR_2=0x0000000020000000,PF2_PCIEBAR2AXIBAR_3=0x0000000000000000,PF2_PCIEBAR2AXIBAR_4=0x0000000000000000,PF2_PCIEBAR2AXIBAR_5=0x0000000000000000,PF2_PCIEBAR2AXIBAR_6=0x0000000000000000,PF3_BAR0_APERTURE_SIZE=0x00,PF3_BAR1_APERTURE_SIZE=0x00,PF3_BAR2_APERTURE_SIZE=0x00,PF3_BAR3_APERTURE_SIZE=0x00,PF3_BAR4_APERTURE_SIZE=0x00,PF3_BAR5_APERTURE_SIZE=0x00,PF3_BAR6_APERTURE_SIZE=0x00,PF3_BAR0_CONTROL=0x0,PF3_BAR1_CONTROL=0x0,PF3_BAR2_CONTROL=0x0,PF3_BAR3_CONTROL=0x0,PF3_BAR4_CONTROL=0x0,PF3_BAR5_CONTROL=0x0,PF3_BAR6_CONTROL=0x0,PF3_SRIOV_BAR0_CONTROL=0x0,PF3_SRIOV_BAR1_CONTROL=0x0,PF3_SRIOV_BAR2_CONTROL=0x0,PF3_SRIOV_BAR3_CONTROL=0x0,PF3_SRIOV_BAR4_CONTROL=0x0,PF3_SRIOV_BAR5_CONTROL=0x0,PF3_PCIEBAR2AXIBAR_0=0x0000000000000000,PF3_PCIEBAR2AXIBAR_1=0x0000000030000000,PF3_PCIEBAR2AXIBAR_2=0x0000000030000000,PF3_PCIEBAR2AXIBAR_3=0x0000000000000000,PF3_PCIEBAR2AXIBAR_4=0x0000000000000000,PF3_PCIEBAR2AXIBAR_5=0x0000000000000000,PF3_PCIEBAR2AXIBAR_6=0x0000000000000000,PF0_VF_BAR0_APERTURE_SIZE=0x00,PF0_VF_BAR1_APERTURE_SIZE=0x00,PF0_VF_BAR2_APERTURE_SIZE=0x00,PF0_VF_BAR3_APERTURE_SIZE=0x00,PF0_VF_BAR4_APERTURE_SIZE=0x00,PF0_VF_BAR5_APERTURE_SIZE=0x00,PF0_VF_BAR6_APERTURE_SIZE=0x00,PF1_VF_BAR0_APERTURE_SIZE=0x00,PF1_VF_BAR1_APERTURE_SIZE=0x00,PF1_VF_BAR2_APERTURE_SIZE=0x00,PF1_VF_BAR3_APERTURE_SIZE=0x00,PF1_VF_BAR4_APERTURE_SIZE=0x00,PF1_VF_BAR5_APERTURE_SIZE=0x00,PF1_VF_BAR6_APERTURE_SIZE=0x00,PF2_VF_BAR0_APERTURE_SIZE=0x00,PF2_VF_BAR1_APERTURE_SIZE=0x00,PF2_VF_BAR2_APERTURE_SIZE=0x00,PF2_VF_BAR3_APERTURE_SIZE=0x00,PF2_VF_BAR4_APERTURE_SIZE=0x00,PF2_VF_BAR5_APERTURE_SIZE=0x00,PF2_VF_BAR6_APERTURE_SIZE=0x00,PF3_VF_BAR0_APERTURE_SIZE=0x00,PF3_VF_BAR1_APERTURE_SIZE=0x00,PF3_VF_BAR2_APERTURE_SIZE=0x00,PF3_VF_BAR3_APERTURE_SIZE=0x00,PF3_VF_BAR4_APERTURE_SIZE=0x00,PF3_VF_BAR5_APERTURE_SIZE=0x00,PF3_VF_BAR6_APERTURE_SIZE=0x00,PF0_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_1=0x0000000040000000,PF0_VF_PCIEBAR2AXIBAR_2=0x0000000040000000,PF0_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_1=0x0000000050000000,PF1_VF_PCIEBAR2AXIBAR_2=0x0000000050000000,PF1_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_1=0x0000000060000000,PF2_VF_PCIEBAR2AXIBAR_2=0x0000000060000000,PF2_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_1=0x0000000070000000,PF3_VF_PCIEBAR2AXIBAR_2=0x0000000070000000,PF3_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,BARLITE1=1,BARLITE2=7,BARLITE_MB_PF0=0,BARLITE_MB_PF1=0,BARLITE_MB_PF2=0,BARLITE_MB_PF3=0,BARLITE_MSIX_PF0=000001,BARLITE_MSIX_PF1=0x00,BARLITE_MSIX_PF2=0x00,BARLITE_MSIX_PF3=0x00,VCU118_BOARD=FALSE,SPLIT_DMA=FALSE,PIPE_LINE_STAGE=2,MULT_PF_DES=FALSE,xlnx_ref_board=None,GTWIZ_IN_CORE=1,GTCOM_IN_CORE=2,INS_LOSS_PROFILE=Add-in_Card,FUNC_MODE=1,PF1_ENABLED=0,PF2_ENABLED=0,PF3_ENABLED=0,DMA_RESET_SOURCE_SEL=0,C_MSIX_INT_TABLE_EN=0,VU9P_TUL_EX=FALSE,XLNX_DDR_EX=FALSE,PCIE_BLK_TYPE=0,CCIX_ENABLE=FALSE,CCIX_DVSEC=FALSE,EXT_SYS_CLK_BUFG=FALSE,C_NUM_OF_SC=1,USR_IRQ_EXDES=FALSE,AXI_VIP_IN_EXDES=FALSE,XDMA_NON_INCREMENTAL_EXDES=FALSE,XDMA_ST_INFINITE_DESC_EXDES=FALSE,EXT_XVC_VSEC_ENABLE=FALSE,ACS_EXT_CAP_ENABLE=FALSE,EN_PCIE_DEBUG_PORTS=FALSE,MULTQ_EN=1,DMA_MM=1,DMA_ST=0,DMA_COMPLETION=0,C_PCIE_PFS_SUPPORTED=1,C_SRIOV_EN=0,BARLITE_EXT_PF0=0x04,BARLITE_EXT_PF1=000000,BARLITE_EXT_PF2=000000,BARLITE_EXT_PF3=000000,BARLITE_INT_PF0=000001,BARLITE_INT_PF1=0x00,BARLITE_INT_PF2=0x00,BARLITE_INT_PF3=0x00,CSR_MODULE=1,NUM_VFS_PF0=4,NUM_VFS_PF1=4,NUM_VFS_PF2=4,NUM_VFS_PF3=4,FIRSTVF_OFFSET_PF0=1,FIRSTVF_OFFSET_PF1=4,FIRSTVF_OFFSET_PF2=7,FIRSTVF_OFFSET_PF3=10,VF_BARLITE_EXT_PF0=0x00,VF_BARLITE_EXT_PF1=0x00,VF_BARLITE_EXT_PF2=0x00,VF_BARLITE_EXT_PF3=0x00,VF_BARLITE_INT_PF0=0x00,VF_BARLITE_INT_PF1=0x00,VF_BARLITE_INT_PF2=0x00,VF_BARLITE_INT_PF3=0x00,C_C2H_NUM_CHNL=4,C_H2C_NUM_CHNL=4,H2C_XDMA_CHNL=0x01,C2H_XDMA_CHNL=0x01,AXISTEN_IF_ENABLE_MSG_ROUTE=0x1EFFF,ENABLE_MORE=FALSE,DISABLE_BRAM_PIPELINE=FALSE,DISABLE_EQ_SYNCHRONIZER=FALSE,C_ENABLE_RESOURCE_REDUCTION=FALSE,GEN4_EIEOS_0S7=TRUE,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_MAX_NUM_QUEUE=512,DSC_BYPASS_RD_CSR=1,DSC_BYPASS_WR_CSR=1,ENABLE_ATS_SWITCH=FALSE,BRIDGE_BURST=FALSE,RQ_RCFG_EN=TRUE,DMA_MODE_EN=FALSE,FLR_ENABLE=FALSE,MAILBOX_ENABLE=FALSE,CFG_SPACE_ENABLE=FALSE,C_LAST_CORE_CAP_ADDR=0x100,C_VSEC_CAP_ADDR=0xE00,CMP_COL_REG_0=1,CMP_COL_REG_1=0,CMP_COL_REG_2=0,CMP_COL_REG_3=0,CMP_COL_REG_4=0,CMP_COL_REG_5=0,CMP_COL_REG_6=0,CMP_COL_REG_7=0,CMP_ERR_REG_0=2,CMP_ERR_REG_1=0,CMP_ERR_REG_2=0,CMP_ERR_REG_3=0,CMP_ERR_REG_4=0,CMP_ERR_REG_5=0,CMP_ERR_REG_6=0,CMP_ERR_REG_7=0,C2H_STREAM_CPL_DATA_SIZE=0,ARI_CAP_ENABLE=false,AXISTEN_IF_MSIX_RX_PARITY_EN=FALSE,PF0_MSIX_VECTORS=1,PF1_MSIX_VECTORS=8,PF2_MSIX_VECTORS=0,PF3_MSIX_VECTORS=0,ADV_INT_USR=FALSE,PCIE_ID_IF=FALSE,MDMA_PFCH_CACHE_DEPTH=16,WRB_COAL_MAX_BUF=16,ENABLE_ERROR_INJECTION=FALSE,ENABLE_AT_PORTS=FALSE,WRB_COAL_LOOP_FIX_DISABLE=0,USE_STANDARD_INTERFACES=TRUE,DMA_2RP=FALSE,VIRTIO_EN=FALSE,MHOST_EN=FALSE,ALF_CAP_ENABLE=FALSE,ASYNC_CLK_ENABLE=FALSE,SOFT_NIC=FALSE,VDM_EN=FALSE,C_M_AXIB_EN=FALSE,SOFT_NIC_BRIDGE=FALSE,USR_IRQ_XDMA_TYPE_INTERFACE=FALSE,C_DBG_EN=DEBUG_NONE,C_DSC_BYP_MODE=NONE,IEP_EN=FALSE,SHELL_BRIDGE=0,MSIX_PCIE_INTERNAL=0,C_AXIBAR_NOTRANSLATE=0,VERSAL_PART_TYPE=SXX,VERSAL_PART_TYPE_HXX=NVD,DATA_MOVER=FALSE,TANDEM_RFSOC=FALSE,PL_DISABLE_LANE_REVERSAL=FALSE,ENABLE_64BIT=TRUE}" *) (* DowngradeIPIdentifiedWarnings = "yes" *)
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/AS02MC04_qdma_enum_qdma_0_0_stub.vhdl (1 usage)
+(124, 11747) attribute CORE_GENERATION_INFO of AS02MC04_qdma_enum_qdma_0_0 : entity is "AS02MC04_qdma_enum_qdma_0_0,AS02MC04_qdma_enum_qdma_0_0_core_top,{x_ipProduct=Vivado 2025.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=qdma,x_ipVersion=5.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,PL_UPSTREAM_FACING=true,TL_LEGACY_MODE_ENABLE=false,PCIE_BLK_LOCN=0,PL_LINK_CAP_MAX_LINK_WIDTH=8,PL_LINK_CAP_MAX_LINK_SPEED=4,REF_CLK_FREQ=0,DRP_CLK_SEL=0,FREE_RUN_FREQ=0,AXI_ADDR_WIDTH=64,AXI_DATA_WIDTH=256,CORE_CLK_FREQ=1,PLL_TYPE=2,USER_CLK_FREQ=2,SILICON_REV=Pre-Production,PIPE_SIM=FALSE,EGW_IS_PARENT_IP=1,EXT_CH_GT_DRP=false,PCIE3_DRP=false,DEDICATE_PERST=true,SYS_RESET_POLARITY=0,MCAP_ENABLEMENT=NONE,EXT_STARTUP_PRIMITIVE=false,RBAR_ENABLE=FALSE,PF0_VENDOR_ID=0x10EE,PF0_DEVICE_ID=0x9038,PF0_REVISION_ID=0x01,PF0_SUBSYSTEM_VENDOR_ID=0x0002,PF0_SUBSYSTEM_ID=0x002A,PF1_VENDOR_ID=0x10EE,PF1_DEVICE_ID=0x913F,PF1_REVISION_ID=0x00,PF1_SUBSYSTEM_VENDOR_ID=0x0002,PF1_SUBSYSTEM_ID=0x0007,PF2_VENDOR_ID=0x10EE,PF2_DEVICE_ID=0x9238,PF2_REVISION_ID=0x00,PF2_SUBSYSTEM_VENDOR_ID=0x10EE,PF2_SUBSYSTEM_ID=0x0007,PF3_VENDOR_ID=0x10EE,PF3_DEVICE_ID=0x9338,PF3_REVISION_ID=0x00,PF3_SUBSYSTEM_VENDOR_ID=0x10EE,PF3_SUBSYSTEM_ID=0x0007,AXILITE_MASTER_APERTURE_SIZE=0x0D,AXILITE_MASTER_CONTROL=0x4,XDMA_APERTURE_SIZE=0x0D,XDMA_CONTROL=0x4,AXIST_BYPASS_APERTURE_SIZE=0x00,AXIST_BYPASS_CONTROL=0x0,PF0_INTERRUPT_PIN=0x1,PF1_INTERRUPT_PIN=0x1,PF2_INTERRUPT_PIN=0x1,PF3_INTERRUPT_PIN=0x1,PF0_MSI_CAP_MULTIMSGCAP=0,C_COMP_TIMEOUT=1,C_TIMEOUT0_SEL=0xE,C_TIMEOUT1_SEL=0xF,C_TIMEOUT_MULT=0x3,C_OLD_BRIDGE_TIMEOUT=0,SHARED_LOGIC=1,SHARED_LOGIC_CLK=false,SHARED_LOGIC_BOTH=false,SHARED_LOGIC_GTC=false,EN_TRANSCEIVER_STATUS_PORTS=FALSE,IS_BOARD_PROJECT=0,EN_GT_SELECTION=FALSE,SELECT_QUAD=GTY_Quad_227,ULTRASCALE=FALSE,ULTRASCALE_PLUS=TRUE,VERSAL=FALSE,V7_GEN3=FALSE,MSI_ENABLED=FALSE,RP_MSI_ENABLED=TRUE,DEV_PORT_TYPE=0,XDMA_AXI_INTF_MM=1,XDMA_PCIE_64BIT_EN=false,XDMA_AXILITE_MASTER=TRUE,XDMA_AXIST_BYPASS=FALSE,XDMA_RNUM_CHNL=4,XDMA_WNUM_CHNL=4,XDMA_AXILITE_SLAVE=FALSE,CSR_AXILITE_SLAVE=FALSE,XDMA_NUM_USR_IRQ=16,XDMA_RNUM_RIDS=32,XDMA_WNUM_RIDS=32,C_M_AXI_ID_WIDTH=4,C_AXIBAR_NUM=1,C_FAMILY=kintexuplus,XDMA_NUM_PCIE_TAG=256,EN_AXI_MASTER_IF=FALSE,XDMA_DSC_BYPASS=FALSE,C_METERING_ON=1,RX_DETECT=0,C_ATS_ENABLE=FALSE,C_ATS_CAP_NEXTPTR=0x000,C_PR_CAP_NEXTPTR=0x000,C_PRI_ENABLE=FALSE,DSC_BYPASS_RD=0,DSC_BYPASS_WR=0,DSC_BYPASS_RD_OUT=0,DSC_BYPASS_WR_OUT=0,XDMA_STS_PORTS=FALSE,MSIX_ENABLED=TRUE,CFG_MGMT_IF=TRUE,RQ_SEQ_NUM_IGNORE=0,CFG_EXT_IF=FALSE,LEGACY_CFG_EXT_IF=FALSE,C_PARITY_PROP=0,EN_DEBUG_PORTS=FALSE,VU9P_BOARD=FALSE,ENABLE_JTAG_DBG=TRUE,ENABLE_IBERT=FALSE,MM_SLAVE_EN=0,DMA_EN=1,C_AXIBAR_0=0x0000000000000000,C_AXIBAR_1=0x0000000000000000,C_AXIBAR_2=0x0000000000000000,C_AXIBAR_3=0x0000000000000000,C_AXIBAR_4=0x0000000000000000,C_AXIBAR_5=0x0000000000000000,C_AXIBAR_HIGHADDR_0=0x0000000000000000,C_AXIBAR_HIGHADDR_1=0x0000000000000000,C_AXIBAR_HIGHADDR_2=0x0000000000000000,C_AXIBAR_HIGHADDR_3=0x0000000000000000,C_AXIBAR_HIGHADDR_4=0x0000000000000000,C_AXIBAR_HIGHADDR_5=0x0000000000000000,C_AXIBAR2PCIEBAR_0=0x0000000000000000,C_AXIBAR2PCIEBAR_1=0x0000000000000000,C_AXIBAR2PCIEBAR_2=0x0000000000000000,C_AXIBAR2PCIEBAR_3=0x0000000000000000,C_AXIBAR2PCIEBAR_4=0x0000000000000000,C_AXIBAR2PCIEBAR_5=0x0000000000000000,MINIMAL_DMA_EN=FALSE,EN_AXI_SLAVE_IF=TRUE,C_INCLUDE_BAROFFSET_REG=1,C_BASEADDR=0x00001000,C_HIGHADDR=0x00001FFF,C_S_AXI_ID_WIDTH=4,C_S_AXI_NUM_READ=32,C_M_AXI_NUM_READ=32,C_S_AXI_NUM_WRITE=32,C_M_AXI_NUM_WRITE=16,MSIX_IMPL_EXT=TRUE,AXI_ACLK_LOOPBACK=FALSE,PCIEBAR_NUM=6,PF0_BAR0_APERTURE_SIZE=0x0B,PF0_BAR1_APERTURE_SIZE=0x00,PF0_BAR2_APERTURE_SIZE=0x05,PF0_BAR3_APERTURE_SIZE=0x00,PF0_BAR4_APERTURE_SIZE=0x00,PF0_BAR5_APERTURE_SIZE=0x00,PF0_BAR6_APERTURE_SIZE=0x00,PF0_BAR0_CONTROL=0x6,PF0_BAR1_CONTROL=0x0,PF0_BAR2_CONTROL=0x6,PF0_BAR3_CONTROL=0x0,PF0_BAR4_CONTROL=0x0,PF0_BAR5_CONTROL=0x0,PF0_BAR6_CONTROL=0x0,PF0_SRIOV_BAR0_CONTROL=0x7,PF0_SRIOV_BAR1_CONTROL=0x0,PF0_SRIOV_BAR2_CONTROL=0x7,PF0_SRIOV_BAR3_CONTROL=0x0,PF0_SRIOV_BAR4_CONTROL=0x0,PF0_SRIOV_BAR5_CONTROL=0x0,PF0_ADDR_MASK=0x0000000000000FFF,PF1_ADDR_MASK=0x0000000000000FFF,PF2_ADDR_MASK=0x0000000000000FFF,PF3_ADDR_MASK=0x0000000000000FFF,PF0_VF_ADDR_MASK=0x0000000000000FFF,PF1_VF_ADDR_MASK=0x0000000000000FFF,PF2_VF_ADDR_MASK=0x0000000000000FFF,PF3_VF_ADDR_MASK=0x0000000000000FFF,C_PCIEBAR2AXIBAR_0=0x0000000000000000,C_PCIEBAR2AXIBAR_1=0x0000000000000000,C_PCIEBAR2AXIBAR_2=0x0000000000000000,C_PCIEBAR2AXIBAR_3=0x0000000000000000,C_PCIEBAR2AXIBAR_4=0x0000000000000000,C_PCIEBAR2AXIBAR_5=0x0000000000000000,C_PCIEBAR2AXIBAR_6=0x0000000000000000,PF1_BAR0_APERTURE_SIZE=0x00,PF1_BAR1_APERTURE_SIZE=0x00,PF1_BAR2_APERTURE_SIZE=0x00,PF1_BAR3_APERTURE_SIZE=0x00,PF1_BAR4_APERTURE_SIZE=0x00,PF1_BAR5_APERTURE_SIZE=0x00,PF1_BAR6_APERTURE_SIZE=0x00,PF1_BAR0_CONTROL=0x0,PF1_BAR1_CONTROL=0x0,PF1_BAR2_CONTROL=0x0,PF1_BAR3_CONTROL=0x0,PF1_BAR4_CONTROL=0x0,PF1_BAR5_CONTROL=0x0,PF1_BAR6_CONTROL=0x0,PF1_SRIOV_BAR0_CONTROL=0x0,PF1_SRIOV_BAR1_CONTROL=0x0,PF1_SRIOV_BAR2_CONTROL=0x0,PF1_SRIOV_BAR3_CONTROL=0x0,PF1_SRIOV_BAR4_CONTROL=0x0,PF1_SRIOV_BAR5_CONTROL=0x0,PF1_PCIEBAR2AXIBAR_0=0x0000000000000000,PF1_PCIEBAR2AXIBAR_1=0x0000000010000000,PF1_PCIEBAR2AXIBAR_2=0x0000000010000000,PF1_PCIEBAR2AXIBAR_3=0x0000000000000000,PF1_PCIEBAR2AXIBAR_4=0x0000000000000000,PF1_PCIEBAR2AXIBAR_5=0x0000000000000000,PF1_PCIEBAR2AXIBAR_6=0x0000000000000000,PF2_BAR0_APERTURE_SIZE=0x00,PF2_BAR1_APERTURE_SIZE=0x00,PF2_BAR2_APERTURE_SIZE=0x00,PF2_BAR3_APERTURE_SIZE=0x00,PF2_BAR4_APERTURE_SIZE=0x00,PF2_BAR5_APERTURE_SIZE=0x00,PF2_BAR6_APERTURE_SIZE=0x00,PF2_BAR0_CONTROL=0x0,PF2_BAR1_CONTROL=0x0,PF2_BAR2_CONTROL=0x0,PF2_BAR3_CONTROL=0x0,PF2_BAR4_CONTROL=0x0,PF2_BAR5_CONTROL=0x0,PF2_BAR6_CONTROL=0x0,PF2_SRIOV_BAR0_CONTROL=0x0,PF2_SRIOV_BAR1_CONTROL=0x0,PF2_SRIOV_BAR2_CONTROL=0x0,PF2_SRIOV_BAR3_CONTROL=0x0,PF2_SRIOV_BAR4_CONTROL=0x0,PF2_SRIOV_BAR5_CONTROL=0x0,PF2_PCIEBAR2AXIBAR_0=0x0000000000000000,PF2_PCIEBAR2AXIBAR_1=0x0000000020000000,PF2_PCIEBAR2AXIBAR_2=0x0000000020000000,PF2_PCIEBAR2AXIBAR_3=0x0000000000000000,PF2_PCIEBAR2AXIBAR_4=0x0000000000000000,PF2_PCIEBAR2AXIBAR_5=0x0000000000000000,PF2_PCIEBAR2AXIBAR_6=0x0000000000000000,PF3_BAR0_APERTURE_SIZE=0x00,PF3_BAR1_APERTURE_SIZE=0x00,PF3_BAR2_APERTURE_SIZE=0x00,PF3_BAR3_APERTURE_SIZE=0x00,PF3_BAR4_APERTURE_SIZE=0x00,PF3_BAR5_APERTURE_SIZE=0x00,PF3_BAR6_APERTURE_SIZE=0x00,PF3_BAR0_CONTROL=0x0,PF3_BAR1_CONTROL=0x0,PF3_BAR2_CONTROL=0x0,PF3_BAR3_CONTROL=0x0,PF3_BAR4_CONTROL=0x0,PF3_BAR5_CONTROL=0x0,PF3_BAR6_CONTROL=0x0,PF3_SRIOV_BAR0_CONTROL=0x0,PF3_SRIOV_BAR1_CONTROL=0x0,PF3_SRIOV_BAR2_CONTROL=0x0,PF3_SRIOV_BAR3_CONTROL=0x0,PF3_SRIOV_BAR4_CONTROL=0x0,PF3_SRIOV_BAR5_CONTROL=0x0,PF3_PCIEBAR2AXIBAR_0=0x0000000000000000,PF3_PCIEBAR2AXIBAR_1=0x0000000030000000,PF3_PCIEBAR2AXIBAR_2=0x0000000030000000,PF3_PCIEBAR2AXIBAR_3=0x0000000000000000,PF3_PCIEBAR2AXIBAR_4=0x0000000000000000,PF3_PCIEBAR2AXIBAR_5=0x0000000000000000,PF3_PCIEBAR2AXIBAR_6=0x0000000000000000,PF0_VF_BAR0_APERTURE_SIZE=0x00,PF0_VF_BAR1_APERTURE_SIZE=0x00,PF0_VF_BAR2_APERTURE_SIZE=0x00,PF0_VF_BAR3_APERTURE_SIZE=0x00,PF0_VF_BAR4_APERTURE_SIZE=0x00,PF0_VF_BAR5_APERTURE_SIZE=0x00,PF0_VF_BAR6_APERTURE_SIZE=0x00,PF1_VF_BAR0_APERTURE_SIZE=0x00,PF1_VF_BAR1_APERTURE_SIZE=0x00,PF1_VF_BAR2_APERTURE_SIZE=0x00,PF1_VF_BAR3_APERTURE_SIZE=0x00,PF1_VF_BAR4_APERTURE_SIZE=0x00,PF1_VF_BAR5_APERTURE_SIZE=0x00,PF1_VF_BAR6_APERTURE_SIZE=0x00,PF2_VF_BAR0_APERTURE_SIZE=0x00,PF2_VF_BAR1_APERTURE_SIZE=0x00,PF2_VF_BAR2_APERTURE_SIZE=0x00,PF2_VF_BAR3_APERTURE_SIZE=0x00,PF2_VF_BAR4_APERTURE_SIZE=0x00,PF2_VF_BAR5_APERTURE_SIZE=0x00,PF2_VF_BAR6_APERTURE_SIZE=0x00,PF3_VF_BAR0_APERTURE_SIZE=0x00,PF3_VF_BAR1_APERTURE_SIZE=0x00,PF3_VF_BAR2_APERTURE_SIZE=0x00,PF3_VF_BAR3_APERTURE_SIZE=0x00,PF3_VF_BAR4_APERTURE_SIZE=0x00,PF3_VF_BAR5_APERTURE_SIZE=0x00,PF3_VF_BAR6_APERTURE_SIZE=0x00,PF0_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_1=0x0000000040000000,PF0_VF_PCIEBAR2AXIBAR_2=0x0000000040000000,PF0_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF0_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_1=0x0000000050000000,PF1_VF_PCIEBAR2AXIBAR_2=0x0000000050000000,PF1_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF1_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_1=0x0000000060000000,PF2_VF_PCIEBAR2AXIBAR_2=0x0000000060000000,PF2_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF2_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_0=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_1=0x0000000070000000,PF3_VF_PCIEBAR2AXIBAR_2=0x0000000070000000,PF3_VF_PCIEBAR2AXIBAR_3=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_4=0x0000000000000000,PF3_VF_PCIEBAR2AXIBAR_5=0x0000000000000000,BARLITE1=1,BARLITE2=7,BARLITE_MB_PF0=0,BARLITE_MB_PF1=0,BARLITE_MB_PF2=0,BARLITE_MB_PF3=0,BARLITE_MSIX_PF0=000001,BARLITE_MSIX_PF1=0x00,BARLITE_MSIX_PF2=0x00,BARLITE_MSIX_PF3=0x00,VCU118_BOARD=FALSE,SPLIT_DMA=FALSE,PIPE_LINE_STAGE=2,MULT_PF_DES=FALSE,xlnx_ref_board=None,GTWIZ_IN_CORE=1,GTCOM_IN_CORE=2,INS_LOSS_PROFILE=Add-in_Card,FUNC_MODE=1,PF1_ENABLED=0,PF2_ENABLED=0,PF3_ENABLED=0,DMA_RESET_SOURCE_SEL=0,C_MSIX_INT_TABLE_EN=0,VU9P_TUL_EX=FALSE,XLNX_DDR_EX=FALSE,PCIE_BLK_TYPE=0,CCIX_ENABLE=FALSE,CCIX_DVSEC=FALSE,EXT_SYS_CLK_BUFG=FALSE,C_NUM_OF_SC=1,USR_IRQ_EXDES=FALSE,AXI_VIP_IN_EXDES=FALSE,XDMA_NON_INCREMENTAL_EXDES=FALSE,XDMA_ST_INFINITE_DESC_EXDES=FALSE,EXT_XVC_VSEC_ENABLE=FALSE,ACS_EXT_CAP_ENABLE=FALSE,EN_PCIE_DEBUG_PORTS=FALSE,MULTQ_EN=1,DMA_MM=1,DMA_ST=0,DMA_COMPLETION=0,C_PCIE_PFS_SUPPORTED=1,C_SRIOV_EN=0,BARLITE_EXT_PF0=0x04,BARLITE_EXT_PF1=000000,BARLITE_EXT_PF2=000000,BARLITE_EXT_PF3=000000,BARLITE_INT_PF0=000001,BARLITE_INT_PF1=0x00,BARLITE_INT_PF2=0x00,BARLITE_INT_PF3=0x00,CSR_MODULE=1,NUM_VFS_PF0=4,NUM_VFS_PF1=4,NUM_VFS_PF2=4,NUM_VFS_PF3=4,FIRSTVF_OFFSET_PF0=1,FIRSTVF_OFFSET_PF1=4,FIRSTVF_OFFSET_PF2=7,FIRSTVF_OFFSET_PF3=10,VF_BARLITE_EXT_PF0=0x00,VF_BARLITE_EXT_PF1=0x00,VF_BARLITE_EXT_PF2=0x00,VF_BARLITE_EXT_PF3=0x00,VF_BARLITE_INT_PF0=0x00,VF_BARLITE_INT_PF1=0x00,VF_BARLITE_INT_PF2=0x00,VF_BARLITE_INT_PF3=0x00,C_C2H_NUM_CHNL=4,C_H2C_NUM_CHNL=4,H2C_XDMA_CHNL=0x01,C2H_XDMA_CHNL=0x01,AXISTEN_IF_ENABLE_MSG_ROUTE=0x1EFFF,ENABLE_MORE=FALSE,DISABLE_BRAM_PIPELINE=FALSE,DISABLE_EQ_SYNCHRONIZER=FALSE,C_ENABLE_RESOURCE_REDUCTION=FALSE,GEN4_EIEOS_0S7=TRUE,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_MAX_NUM_QUEUE=512,DSC_BYPASS_RD_CSR=1,DSC_BYPASS_WR_CSR=1,ENABLE_ATS_SWITCH=FALSE,BRIDGE_BURST=FALSE,RQ_RCFG_EN=TRUE,DMA_MODE_EN=FALSE,FLR_ENABLE=FALSE,MAILBOX_ENABLE=FALSE,CFG_SPACE_ENABLE=FALSE,C_LAST_CORE_CAP_ADDR=0x100,C_VSEC_CAP_ADDR=0xE00,CMP_COL_REG_0=1,CMP_COL_REG_1=0,CMP_COL_REG_2=0,CMP_COL_REG_3=0,CMP_COL_REG_4=0,CMP_COL_REG_5=0,CMP_COL_REG_6=0,CMP_COL_REG_7=0,CMP_ERR_REG_0=2,CMP_ERR_REG_1=0,CMP_ERR_REG_2=0,CMP_ERR_REG_3=0,CMP_ERR_REG_4=0,CMP_ERR_REG_5=0,CMP_ERR_REG_6=0,CMP_ERR_REG_7=0,C2H_STREAM_CPL_DATA_SIZE=0,ARI_CAP_ENABLE=false,AXISTEN_IF_MSIX_RX_PARITY_EN=FALSE,PF0_MSIX_VECTORS=1,PF1_MSIX_VECTORS=8,PF2_MSIX_VECTORS=0,PF3_MSIX_VECTORS=0,ADV_INT_USR=FALSE,PCIE_ID_IF=FALSE,MDMA_PFCH_CACHE_DEPTH=16,WRB_COAL_MAX_BUF=16,ENABLE_ERROR_INJECTION=FALSE,ENABLE_AT_PORTS=FALSE,WRB_COAL_LOOP_FIX_DISABLE=0,USE_STANDARD_INTERFACES=TRUE,DMA_2RP=FALSE,VIRTIO_EN=FALSE,MHOST_EN=FALSE,ALF_CAP_ENABLE=FALSE,ASYNC_CLK_ENABLE=FALSE,SOFT_NIC=FALSE,VDM_EN=FALSE,C_M_AXIB_EN=FALSE,SOFT_NIC_BRIDGE=FALSE,USR_IRQ_XDMA_TYPE_INTERFACE=FALSE,C_DBG_EN=DEBUG_NONE,C_DSC_BYP_MODE=NONE,IEP_EN=FALSE,SHELL_BRIDGE=0,MSIX_PCIE_INTERNAL=0,C_AXIBAR_NOTRANSLATE=0,VERSAL_PART_TYPE=SXX,VERSAL_PART_TYPE_HXX=NVD,DATA_MOVER=FALSE,TANDEM_RFSOC=FALSE,PL_DISABLE_LANE_REVERSAL=FALSE,ENABLE_64BIT=TRUE}";
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/ip/AS02MC04_qdma_enum_qdma_0_0/synth/AS02MC04_qdma_enum_qdma_0_0.sv (2 usages)
+(78, 170) ONE,IEP_EN=FALSE,SHELL_BRIDGE=0,MSIX_PCIE_INTERNAL=0,C_AXIBAR_NOTRANSLATE=0,VERSAL_PART_TYPE=SXX,VERSAL_PART_TYPE_HXX=NVD,DATA_MOVER=FALSE,TANDEM_RFSOC=FALSE,PL_DISABLE_LANE_REVERSAL=FALSE,ENABLE_64BIT=TRUE}" *)
+(866, 17) .PL_DISABLE_LANE_REVERSAL("FALSE"),
+/home/mr_halfword/fpga_sio/fpga_tests/AS02MC04_qdma_enum/gen3_x8_reversed_lane_order_reversal_enabled/AS02MC04_qdma_enum/AS02MC04_qdma_enum.gen/sources_1/bd/AS02MC04_qdma_enum/hw_handoff/AS02MC04_qdma_enum.hwh (3 usages)
+(676, 37) <PARAMETER NAME="PL_DISABLE_LANE_REVERSAL" VALUE="FALSE"/>
+(796, 37) <PARAMETER NAME="PL_DISABLE_LANE_REVERSAL_NV" VALUE="false"/>
(999, 26) <PARAMETER NAME="lane_reversal" VALUE="false"/>The PL_DISABLE_LANE_REVERSAL parameter to the xilinx.com:ip:pcie4_uscale_plus:1.3 block is modified by the QDMA Enable Lane Reversal checkbox.
This can enumerate after loading over JTAG, as x4 width on physical slot 5-2. After the PC had booted only enumerated on the 3rd attempt to load over JTAG.
If reboot with the design loaded, the link goes down and doesn't come up at reboot.
For this design set the Enable Lane Reversal checkbox in the QDMA configuration. It can enumerate after loading over JTAG, as x4 width on physical slot 5-2.
If reboot with the design loaded:
a. As reboot the link LED goes down and comes back after about one second.
b. After has rebooted can bind vfio-pci to the device.
c. dump_pci_info_pciutils shows the device OK:
domain=0000 bus=2d dev=00 func=00 rev=02
vendor_id=10ee (Xilinx Corporation) device_id=9038 (Device 9038) subvendor_id=0002 subdevice_id=002a
iommu_group=86
driver=vfio-pci
module=vfio_pci
physical_slot=5-2
numa_node=0
control: I/O- Mem- BusMaster- ParErr+ SERR+ DisINTx-
status: INTx- <ParErr- >TAbort- <TAbort- <MAbort- >SERR- DetParErr-
bar[0] base_addr=9b100000 size=40000 is_IO=0 is_prefetchable=0 is_64=1
bar[2] base_addr=9b140000 size=1000 is_IO=0 is_prefetchable=0 is_64=1
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D3 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [70] PCI Express v2 Express Endpoint, MSI 0
Link capabilities: Max speed 8 GT/s Max width x8
Negotiated link status: Current speed 8 GT/s Width x4
Link capabilities2: Supported link speeds 2.5 GT/s 5.0 GT/s 8.0 GT/s
DevCap: MaxPayload 1024 bytes PhantFunc 0 Latency L0s Maximum of 64 ns L1 Maximum of 1 μs
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
DevCtl: CorrErr- NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port # 0 ASPM not supported
L0s Exit Latency More than 4 μs
L1 Exit Latency More than 64 μs
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- ABWMgmt-
LnkSta: TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [100 v1] Advanced Error Reporting
Capabilities: [1c0 v1] Secondary PCIe Capability
Capabilities: [200 v1] Virtual Channel Capability
domain=0000 bus=2c dev=00 func=00 rev=04
vendor_id=8086 (Intel Corporation) device_id=2030 (Sky Lake-E PCI Express Root Port A)
iommu_group=74
driver=pcieport
physical_slot=5
numa_node=0
control: I/O+ Mem+ BusMaster+ ParErr+ SERR+ DisINTx+
status: INTx- <ParErr- >TAbort- <TAbort- <MAbort- >SERR- DetParErr-
Capabilities: [40] Bridge subsystem vendor/device ID
Capabilities: [60] Message Signaled Interrupts
Capabilities: [90] PCI Express v2 Root Port, MSI 0
Link capabilities: Max speed 8 GT/s Max width x4
Negotiated link status: Current speed 8 GT/s Width x4
Link capabilities2: Supported link speeds 2.5 GT/s 5.0 GT/s 8.0 GT/s
DevCap: MaxPayload 256 bytes PhantFunc 0 Latency L0s Maximum of 64 ns L1 Maximum of 1 μs
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
DevCtl: CorrErr- NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop-
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port # 9 ASPM not supported
L0s Exit Latency 256 ns to less than 512 ns
L1 Exit Latency 8 μs to less than 16 μs
ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- ABWMgmt-
LnkSta: TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise-
Slot #5 PowerLimit 0.000W Interlock- NoCompl-
Capabilities: [e0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v1] Vendor-Specific
Capabilities: [110 v1] Access Control Services
Capabilities: [148 v1] Advanced Error Reporting
d. However, running display_identified_pcie_fpga_designs shows the devices reads all ones:
[mr_halfword@skylake-alma ~]$ ~/fpga_sio/software_tests/eclipse_project/bin/release/identify_pcie_fpga_design/display_identified_pcie_fpga_designs
Opening device 0000:15:00.0 (10ee:7024) with IOMMU group 41
Enabled bus master for 0000:15:00.0
Opening device 0000:2d:00.0 (10ee:9038) with IOMMU group 86
Opening device 0000:37:00.0 (10ee:7011) with IOMMU group 87
Enabled bus master for 0000:37:00.0
Design dma_blkram (TEF1001):
PCI device 0000:15:00.0 rev 00 IOMMU group 41 physical slot 3-1
DMA bridge bar 0 memory base offset 0x0 size 0x120000
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
H2C 1 1 1 64
C2H 0 1 1 64
C2H 1 1 1 64
Design AS02MC04_qdma_enum:
PCI device 0000:2d:00.0 rev 02 IOMMU group 86 physical slot 5-2
rtl_version :
vivado_release :
ip_type :
device_type :
User access build timestamp : FFFFFFFF - 31/15/2063 31:63:63
Design Nitefury Project-0 version 0x2:
PCI device 0000:37:00.0 rev 00 IOMMU group 87 physical slot 6-1
DMA bridge bar 2 memory base offset 0x0 size 0x40000000
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
C2H 0 1 1 64
Quad SPI registers at bar 0 offset 0x10000
XADC registers at bar 0 offset 0x3000
e. dump_pci_info_pciutils shows the device reading all ones:
domain=0000 bus=2d dev=00 func=00 rev=ff
vendor_id=10ee (Xilinx Corporation) device_id=9038 (Device 9038)
iommu_group=86
driver=vfio-pci
module=vfio_pci
physical_slot=5-2
numa_node=0
control: I/O+ Mem+ BusMaster+ ParErr+ SERR+ DisINTx+
status: INTx+ <ParErr+ >TAbort+ <TAbort+ <MAbort+ >SERR+ DetParErr+
bar[0] base_addr=9b100000 size=40000 is_IO=0 is_prefetchable=0 is_64=1
bar[2] base_addr=9b140000 size=1000 is_IO=0 is_prefetchable=0 is_64=1
Capabilities: [ff] Unknown encoding 0xff
domain=0000 bus=2c dev=00 func=00 rev=04
vendor_id=8086 (Intel Corporation) device_id=2030 (Sky Lake-E PCI Express Root Port A)
iommu_group=74
driver=pcieport
physical_slot=5
numa_node=0
control: I/O+ Mem+ BusMaster+ ParErr+ SERR+ DisINTx+
status: INTx- <ParErr- >TAbort- <TAbort- <MAbort- >SERR- DetParErr-
Capabilities: [40] Bridge subsystem vendor/device ID
Capabilities: [60] Message Signaled Interrupts
Capabilities: [90] PCI Express v2 Root Port, MSI 0
Link capabilities: Max speed 8 GT/s Max width x4
Negotiated link status: Current speed 2.5 GT/s Width x0
Link capabilities2: Supported link speeds 2.5 GT/s 5.0 GT/s 8.0 GT/s
DevCap: MaxPayload 256 bytes PhantFunc 0 Latency L0s Maximum of 64 ns L1 Maximum of 1 μs
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
DevCtl: CorrErr- NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop-
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port # 9 ASPM not supported
L0s Exit Latency 256 ns to less than 512 ns
L1 Exit Latency 8 μs to less than 16 μs
ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- ABWMgmt-
LnkSta: TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise-
Slot #5 PowerLimit 0.000W Interlock- NoCompl-
Capabilities: [e0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v1] Vendor-Specific
Capabilities: [110 v1] Access Control Services
Capabilities: [148 v1] Advanced Error Reporting
f. Reload over JTAG, and then display_identified_pcie_fpga_designs is able to read the device OK.
Perhaps the first PCIe Hot Reset after a reboot introduces an error.
Using AS02MC04_enum/gen3_x8_example_lane_order never enumerated. Therefore, enabling lane reversal did have some effect, albeit AS02MC04_qdma_enum/gen3_x8_example_lane_order_reversal_enabled doesn't enumerate after every attempt and only enumerated at x4 width.
Trying different PCIe lane mappings. The design used hasn't been committed.
This fails to enumerate, either after loading over JTAG or rebooting:
set_property PACKAGE_PIN P2 [get_ports {pcie_7x_mgt_rxp[3]}]
set_property PACKAGE_PIN T2 [get_ports {pcie_7x_mgt_rxp[2]}]
set_property PACKAGE_PIN V2 [get_ports {pcie_7x_mgt_rxp[1]}]
set_property PACKAGE_PIN Y2 [get_ports {pcie_7x_mgt_rxp[0]}]
set_property PACKAGE_PIN AB2 [get_ports {pcie_7x_mgt_rxp[4]}]
set_property PACKAGE_PIN AD2 [get_ports {pcie_7x_mgt_rxp[5]}]
set_property PACKAGE_PIN AE4 [get_ports {pcie_7x_mgt_rxp[6]}]
set_property PACKAGE_PIN AF2 [get_ports {pcie_7x_mgt_rxp[7]}]This fails to enumerate, either after loading over JTAG or rebooting:
set_property PACKAGE_PIN P2 [get_ports {pcie_7x_mgt_rxp[3]}]
set_property PACKAGE_PIN T2 [get_ports {pcie_7x_mgt_rxp[2]}]
set_property PACKAGE_PIN V2 [get_ports {pcie_7x_mgt_rxp[1]}]
set_property PACKAGE_PIN Y2 [get_ports {pcie_7x_mgt_rxp[0]}]
set_property PACKAGE_PIN AB2 [get_ports {pcie_7x_mgt_rxp[7]}]
set_property PACKAGE_PIN AD2 [get_ports {pcie_7x_mgt_rxp[6]}]
set_property PACKAGE_PIN AE4 [get_ports {pcie_7x_mgt_rxp[5]}]
set_property PACKAGE_PIN AF2 [get_ports {pcie_7x_mgt_rxp[4]}]This enumerated after loading over JTAG, as x4 width on physical slot 5-2. If reboot with the design loaded, the link goes down and doesn't come up at reboot:
set_property PACKAGE_PIN P2 [get_ports {pcie_7x_mgt_rxp[4]}]
set_property PACKAGE_PIN T2 [get_ports {pcie_7x_mgt_rxp[5]}]
set_property PACKAGE_PIN V2 [get_ports {pcie_7x_mgt_rxp[6]}]
set_property PACKAGE_PIN Y2 [get_ports {pcie_7x_mgt_rxp[7]}]
set_property PACKAGE_PIN AB2 [get_ports {pcie_7x_mgt_rxp[0]}]
set_property PACKAGE_PIN AD2 [get_ports {pcie_7x_mgt_rxp[1]}]
set_property PACKAGE_PIN AE4 [get_ports {pcie_7x_mgt_rxp[2]}]
set_property PACKAGE_PIN AF2 [get_ports {pcie_7x_mgt_rxp[3]}]This was trying one lane at a time to find which enumerated. The design used hasn't been committed.
For the following enumerated with no physical slot set. If reboot with the design loaded, the link comes back up. If reboot with the design loaded, the PC reboots. HotPlug- is reported on the Root Port domain=0000 bus=2c dev=01 func=00 rev=04, which explains the reboot.
set_property PACKAGE_PIN P2 [get_ports {pcie_7x_mgt_rxp[0]}]set_property PACKAGE_PIN Y2 [get_ports {pcie_7x_mgt_rxp[0]}]
Looking at the PCIe root ports for slot 5:
domain=0000 bus=2c dev=00 func=00 rev=04(Sky Lake-E PCI Express Root Port A) forphysical_slot=5hasHotPlug+. AS02MC04_enum/gen3_x4_quad224_reversed_lane_order is an example of a design which used this root port and therefore had Hot Plug enabled.domain=0000 bus=2c dev=01 func=00 rev=04(Sky Lake-E PCI Express Root Port B) forphysical_slot=5-1hasHotPlug-.
set_property PACKAGE_PIN AF2 [get_ports {pcie_7x_mgt_rxp[0]}] and set_property PACKAGE_PIN AB2 [get_ports {pcie_7x_mgt_rxp[0]}] enumerated with physical slot 5-2, when either loaded bia JTAG or the PC rebooted.
The following result in the design not enumerating, when try either loading over JTAG or rebooting the PC:
set_property PACKAGE_PIN AE4 [get_ports {pcie_7x_mgt_rxp[0]}]set_property PACKAGE_PIN AD2 [get_ports {pcie_7x_mgt_rxp[0]}]set_property PACKAGE_PIN V2 [get_ports {pcie_7x_mgt_rxp[0]}]set_property PACKAGE_PIN T2 [get_ports {pcie_7x_mgt_rxp[0]}]
For the above the initial thought was that the PCIe lanes were somehow incorrect in the constraints. However, that investigation didn't lead to finding a PCIe lane mapping which resolved the issue.
Therefore, try and check the PCI_PERSTN signal in the HP Z4 G4.
For reference, modified the TEF1001_dma_stream_crc64 design to add a ILA to monitor:
- PCI_PERSTN which is the active low reset input from the PCI slot.
- xdma_0_axi_aresetn whici is the active low reset output from the XMDA.
Configured the ILA with the maximum depth of 131072. Since a reset can last for millisconds set the ILA clock to 2 MHz. Since the PCIe reference clock may not be running when the BIOS asserts PCI_PERSTN used the 200 MHz DDR3 clock as the source clock and a Clocking Wizard to generate a 2 MHz clock:
-
2 MHz is about the lowest possible for the ILA. In the JTAG probe properties set the Frequency to the minimum possible of 750 KHz. That means the ILA clock frequency is > 2.5 times the JTAG clock frequency. When didn't lower the JTAG clock frequency the ILA operation was intermitient. E.g. after attempting to start the ILA triggered unexpectidely and got the error
Data read from hw_ila [hw_ila_1] is corrupted. Unable to upload waveform.63292 - Vivado 2014.4 - Logic Debug - Digilent Cable at 20Mhz ILA not Triggering says:When trying to trigger a design with a frequency clock slower than 2.5x the JTAG clock frequency, the ILA does not trigger.
See also Why is Xilinx ILA's clock frequency required to be at least twice of that of JTAG?
-
To get the Clock Wizard to generate a 2 MHz output had to Allow Override Mode and check CLKOUT4_CASCADE. See How to generate frequency of 30 KHz using clocking wizard IP for ultrascale board. Selected Override Mode:
And after manually selecting the divides got clk_out5 as 2 MHz:
For reset durations:
- When run a program which generates a PCIe Hot Reset at VFIO open xdma_0_axi_aresetn is asserted for 58 ms.
- When reboot the PC:
- PCI_PERSTN is asserted for 20.8 or 21.4 ms (a sample of two reboots).
- xdma_0_axi_aresetn asserts when PCI_PERSTN asserts, but xdma_0_axi_aresetn remains asserted 65 ms at the end of the ILA capture is. I.e. can't see when xdma_0_axi_aresetn de-asserts during a reboot of the PC.
The AS02MC04_dma_stream_crc64 was modified to add a ILA for the PCIe reset, similar to as done for TEF1001_dma_stream_crc64. Used the 100 MHz differential clock as the source for the 2 MHz ILA clock.
Also corrected the IOSTANDARD for the LED and PCI_PERSTN to be LVCMOS33 to match the VCCO measured with SYSMON. That didn't fix the PCIe enumeration issues.
For reset durations:
- When run a program which generates a PCIe Hot Reset at VFIO open xdma_0_axi_aresetn is asserted for 58 ms.
- When reboot the PC:
- PCI_PERSTN is asserted for 20.8 or 20.6 ms (a sample of two reboots).
- xdma_0_axi_aresetn asserts when PCI_PERSTN asserts, but xdma_0_axi_aresetn remains asserted 65 ms at the end of the ILA capture is. I.e. can't see when xdma_0_axi_aresetn de-asserts during a reboot of the PC.
This shows PCI_PERSTN is connected to the expected FPGA pin A9, since the measured reset duration matches that from the TEF1001 board which does enumerate OK.
To confirm the PCIe reference clock pin used, will try different constraints using the AS02MC04_enum/gen3_x8_reversed_lane_order design in the HP Z4 G4.
| Pin constraint | Pin Name | Comment |
|---|---|---|
| T7 | MGTREFCLK1P_225 | The original pin constraint from part0_pins.xml. Enumerates as x4 speed 8 GT/s on physical slot 5-2 when loaded over JTAG. When reboot with the design loaded link goes down and doesn't come back up. |
| V7 | MGTREFCLK0P_225 | Failed to enumerate after loading over JTAG or after a reboot |
| AB7 | MGTREFCLK0P_224 | Failed to enumerate after loading over JTAG or after a reboot |
| Y7 | MGTREFCLK1P_224 | Failed to enumerate after loading over JTAG or after a reboot |
This shows the original pin constraint was correct.
For AS02MC04_enum/AS02MC04_enum built with the PCIe reference clock constaint set to:
# @todo actually 156.25 MHz for SFP+. Used this to see if can use a reference clock
# from a different clock and meet timing.
set_property PACKAGE_PIN K7 [get_ports {CLK_PCIe_100MHz_clk_p[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets AS02MC04_enum_i/util_ds_buf_0/U0/IBUF_OUT[0]]
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets AS02MC04_enum_i/util_ds_buf_0/U0/IBUF_OUT[0]]The CLOCK_DEDICATED_ROUTE properties were set from the errors reported after the initial attempt to just set the package pin. There were some setup violations on 4 paths, worst case -0.033 ns. To actually get the design to work with a non-standard PCIe reference clock frequency would need to:
- Modify the GT setup to change the reference clock frequency.
- Untick "Enable Slot Clock Configuration" in the XDMA configuration, since the PCIe reference clock will now be asynchronous to the slot clock.
The measures the IO bank voltages by using the AS02MC04_dma_stream_crc64 design with different SYSMON configurations and running display_sensor_values to get the values.
| User supply | Bank | Supply | Measurement |
|---|---|---|---|
| 0 | 226 | AVCC | 0.8936V |
| 1 | 226 | AVTT | 1.1953V |
| 2 | 65 | VCCO | 1.8018V |
| 3 | 87 | VCCO | 3.3164V |
| User supply | Bank | Supply | Measurement |
|---|---|---|---|
| 0 | 227 | AVCC | 0.8936V |
| 1 | 226 | MGTVCCAUX | 1.7988V |
| 2 | 86 | VCCO | 3.3105V |
| 3 | 67 | VCCO | 1.7988V |
| User supply | Bank | Supply | Measurement |
|---|---|---|---|
| 0 | 224 | AVCC | 0.8906V |
| 1 | 225 | AVTT | 1.1953V |
| 2 | 66 | ACCAUX | 1.8018V |
| 3 | 64 | VCCO | 1.8018V |
| User supply | Bank | Supply | Measurement |
|---|---|---|---|
| 0 | 224 | AVTT | 1.1924V |
| 1 | 225 | AVCC | 0.8906V |
| 2 | 84 | VCCO | 3.3105V |
| 3 | 86 | VCCINT | 0.8525V |
https://github.com/Chester-Gillon/fpga_sio/blob/main/AS02MC04/constraints/leds.xdc set the IOSTANDARD for the LEDs as LVCMOS18, based upon the constraints from https://github.com/TiferKing/as02mc04_hack/blob/main/as02mc04/1.0/part0_pins.xml. LED_R is on bank 87 which has measured a VCCO of 3.3V.
https://github.com/Chester-Gillon/fpga_sio/blob/main/AS02MC04/constraints/pcie.xdc set the IOSTANDARD for PCI_PERSTN as LVCMOS18, based upon the constraints from https://github.com/TiferKing/as02mc04_hack/blob/main/as02mc04/1.0/part0_pins.xml. PCI_PERSTN is on bank 86 which has measured a VCCO of 3.3V.
I.e. the IOSTANDARD used in the constraints should be corrected.