bit-hack

#include <Arduino.h>
#include <SPI.h>

// for the pinPeripheral() function
#include <wiring_private.h>

#ifndef _ICECLASS_DOPPLER_
#define _ICECLASS_DOPPLER_

#define SPI_FPGA_SPEED 34000000

bit-hack

#include <stdio.h>
#include <stdlib.h>

#include "file.h"


bool file_load(const char *path, file_t *out) {

  if (out->data) {
    file_unload(out);

bit-hack

#include <cassert>
#include <cstdint>
#include <cmath>
#include <algorithm>
#include <array>

#define _SDL_main_h
#include <SDL/SDL.h>

struct app_t {

bit-hack

void span( float x0, float y0 )
{
  // blah
}

void raster( vec2 point[3] )
{
  std::array<mut::vec2, 3> p = {
    point[0], point[1], point[2]
  };

bit-hack

// for the line from [x0,y0] -> [x1,y1]
// given y solve for sx (point on line)
// given x solve for sy (point on line)

const float dx = x1 - x0;
const float dy = y1 - y0;

const float sx = x0 + (y*dx - y0*dx) / dy;
const float sy = y0 + (x*dy - x0*dy) / dx;

bit-hack

std::string base_path(std::string in) {
  const size_t last1 = in.rfind('/');
  const size_t last2 = in.rfind('\\');
  const size_t last = std::max(last1 == std::string::npos ? 0 : last1,
                               last2 == std::string::npos ? 0 : last2);
  in.resize(last);
  return in;
}

bit-hack

`default_nettype none
`timescale 1ns / 1ps


// 640x480 vga generator
// clk = 25Mhz
module vga_t(input i_clk,
             output reg o_hsync,
             output reg o_vsync,
             output reg [9:0] o_x,

bit-hack

# ##############################################################################
# iCEcube PCF
# Version:            2014.12.27052
# File Generated:     Apr 27 2015 09:46:33
# Family & Device:    iCE40HX1K
# Package:            VQ100
# ##############################################################################

### Main FPGA Clock
set_io i_Clk 15

bit-hack

`default_nettype none
`timescale 1ns / 1ps

module seven_seg(input [3:0] val, output reg [6:0] seg);

//            seg
//                 
//          +--0--+
//          5     1
//          +--6--+

bit-hack

`default_nettype none
`timescale 1ns / 1ps

module rom16x256(
    input in_clk,
    input in_rst,
    input [7:0] in_addr,
    output [15:0] out_data);

    assign out_data = rom[ in_addr ];