- Website: https://www.siliconfrog.co.uk/
- Schematics: https://www.siliconfrog.co.uk/PDF/FPGA384/FPGA384_Schematic.pdf
- Github: https://github.com/siliconfrog/fpga-384
16Mhz clock on IOL_5A
`timescale 1 ns / 1 ps | |
module power_on_reset(input in_clk, output out_rst); | |
reg [5:0] reset_cnt = 0; | |
wire resetn = &reset_cnt; | |
assign out_rst = !resetn; | |
always @(posedge in_clk) begin |
// | |
// | |
// | |
module UDA1334( | |
input iCLK, | |
input [15:0] iLeft, | |
input [15:0] iRight, | |
output oSEL, | |
output oCLK, | |
output oDAT); |
16Mhz clock on IOL_5A
`default_nettype none | |
`timescale 1ns / 1ps | |
module i2s_master(input CLK, | |
input [15:0] LIN, | |
input [15:0] RIN, | |
output LRCLK, | |
output DATA, | |
output BCLK); |
/* .__ .__ | |
* ______ ___________|__|____ | | | |
* / ___// __ \_ __ \ \__ \ | | | |
* \___ \\ ___/| | \/ |/ __ \| |__ | |
* /____ >\___ >__| |__(____ /____/ | |
* \/ \/ \/ | |
*/ | |
#define WIN32_LEAN_AND_MEAN | |
#include <Windows.h> |
`default_nettype none | |
`timescale 1ns / 1ps | |
module uart_tx( | |
input clk, // Master clock | |
input rst, // Synchronous reset | |
input [7:0] tx_byte, // Byte to transmit | |
input start, // Start | |
output tx // transmit pin |
`default_nettype none | |
`timescale 1ns / 1ps | |
module top(input CLK, output D5); | |
wire pll_clk_out; | |
wire BYPASS; | |
wire RESETB; | |
wire LOCKED; | |
wire global_clk; |
// http://download.microsoft.com/download/f/f/e/ffef50a5-07dd-4cf8-aaa3-442c0673a029/Virtual%20Hard%20Disk%20Format%20Spec_10_18_06.doc | |
// footer lives at end of the file - 512/511 bytes | |
struct vhd_footer_t { | |
// "conectix" | |
uint64_t cookie; | |
// 0 - No features enabled |
#include <stdio.h> | |
int main(const int argc, const char **args) { | |
if (argc < 4) { | |
printf("usage: %s even.bin odd.bin out.bin", args[0]); | |
return 1; | |
} | |
FILE *odd = NULL; |
extern "C" void test(); | |
#pragma comment(linker, "/alternatename:_test=??0CppLibraryClass@@QAE@XZ") | |
test(); // will call mangled name |